X9520_06 Datasheet, PDF (3/30 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

Pin Configuration
X9520
R_H2
R_W2
R_L2
V3
V3RO
MR
WP
SCL
SDA
V_SS
20 Pin TSSOP
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V1/Vcc
V1RO
V2RO
V2
R_L0
R_W0
R_H0
R_H1
R_W1
R_L1
CSP
1
2
3
4
A ^{V2RO V1/Vcc RW2 RL2}
V2 _V1RO R_{H2 V3}
B
C ^{RW0 RL0 V3RO WP}
R_H1 R_{H0 MR} SCL
D
V_SS R_W1 R_{L1 SDA}
E
Top View – Bumps Down
NOT TO SCALE
Pin Descriptions
TSSOP CSP NAME
FUNCTION
1
B3
R_H2 Connection to end of resistor array for (the 256 Tap) DCP 2.
2
A3
R_w2 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
3
A4
R_L2 Connection to other end of resistor array for (the 256 Tap) DCP 2.
4
B4
V3 V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher
than the V_TRIP3 threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to V_SS when not used.
5
C3 V3RO V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than V_TRIP3 and
goes LOW when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an
external “pull-up” resistor.
6
D3
MR Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO
pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time t_purst after MR has returned to it’s normally LOW
state. The reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the
use of an external “pull-down” resistor.
7
C4
WP Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In
the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and
the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile)
operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled
Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection
feature is disabled.
8
D4 SCL Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
9
E4 SDA Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA
pin input buffer is always active (not gated). This pin requires an external pull up resistor.
10
E1
Vss Ground.
11
E3
R_L1 Connection to other end of resistor for (the 100 Tap) DCP 1.
12
E2
R_w1 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
13
D1
R_H1 Connection to end of resistor array for (the 100 Tap) DCP 1.
14
D2
R_H0 Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
15
C1
R_W0 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
16
C2
R_L0 Connection to the other end of resistor array for (the 64 Tap) DCP 0.
17
B1
V2 V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater
than the V_TRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to V_SS when not used.
3
FN8206.1
January 3, 2006