X9520_06 Datasheet, PDF (23/30 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

SCL
SDA IN
WP
START
X9520
Clk 1
Clk 9
t_SU:WP
t_HD:WP
FIGURE 28. WP PIN TIMING
SCL
SDA
8th bit of last byte
ACK
t_WC
Stop
Condition
FIGURE 29. WRITE CYCLE TIMING
Start
Condition
V1/Vcc
0V
V1RO
0V
MR
0V
t
R
t
PURST
t_RPD
t
PURST
tF
V _TRIP1
t_RPD
FIGURE 30. POWER-UP AND POWER-DOWN TIMING
23
FN8206.1
January 3, 2006