X9520_06 Datasheet, PDF (14/30 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
SCL
SDA
S 1 0 1 0 0 1 0 R/W A 1
T
C
A
K
R
T
SLAVE ADDRESS BYTE
1 11 1 1 1 1
ADDRESS BYTE
A CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 A S
C
CT
K
KO
CONSTAT REGISTER DATA IN
P
FIGURE 18. CONSTAT REGISTER WRITE COMMAND SEQUENCE
The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to the
CONSTAT register:
POR1
0
0
1
1
POR0
0
1
0
1
POWER-ON RESET DELAY (T_PUV1RO)
50ms
100ms (Default)
200ms
300ms
The default for these bits are POR1 = 0, POR0 = 1.
V2OS, V3OS: VOLTAGE MONITOR STATUS BITS
(VOLATILE)
Bits V2OS and V3OS of the CONSTAT register are latched,
volatile flag bits which indicate the status of the Voltage
Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x = 2,3) bits default to the value “0”.
These bits can be set to a “1” by writing the appropriate value to
the CONSTAT register. To provide consistency between the
VxRO and VxOS however, the status of the VxOS bits can only
be set to a “1” when the corresponding VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be reset to
“0” if:
• The device is powered down, then back up
• The corresponding VxRO output becomes LOW
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave Address
set to 1010010 (Refer to Figure 4.). Following the Slave
Address Byte, access to the CONSTAT register requires an
Address Byte which must be set to FFh. Only one data byte
is allowed to be written for each CONSTAT register Write
operation. The user must issue a STOP, after sending this
byte to the register, to initiate the nonvolatile cycle that
stores the BP1, BP0, POR1 and POR0 bits. The X9520 will
not ACKNOWLEDGE any data bytes written after the first
byte is entered (Refer to Figure 18.).
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with the
whole sequence requiring 3 steps.
• Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so there
is no delay after the write. (Operation preceded by a
START and ended with a STOP).
• Write a 06H to the CONSTAT Register to set the Register
Write Enable Latch (RWEL) AND the WEL bit. This is also a
volatile cycle. The zeros in the data byte are required.
(Operation preceded by a START and ended with a STOP).
• Write a one byte value to the CONSTAT Register that has
all the bits set to the desired state. The CONSTAT register
can be represented as qxyst01r in binary, where xy are the
Voltage Monitor Output Status (V2OS and V3OS) bits, st
are the Block Lock Protection (BL1 and BL0) bits, and qr
are the Power-on Reset delay time (t_PUV1RO) control bits
(POR1 - POR0). This operation is proceeded by a START
and ended with a STOP bit. Since this is a nonvolatile
write cycle, it will typically take 5ms to complete. The
RWEL bit is reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2 is set
to ‘1’ in this third step (qxys t11r) then the RWEL bit is set,
but the V2OS, V3OS, POR1, POR0, BL1 and BL0 bits
remain unchanged. Writing a second byte to the control
register is not allowed. Doing so aborts the write operation
and the X9520 does not return an ACKNOWLEDGE.
For example, a sequence of writes to the device CONSTAT
register consisting of [02H, 06H, 02H] will reset all of the
nonvolatile bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin of
the X9520 is active (HIGH) (See "WP: Write Protection Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at any time
by performing a random read (See Figure 19). Using the Slave
Address Byte set to 10100101, and an Address Byte of FFh.
Only one byte is read by each register read operation. The
X9520 resets itself after the first byte is read. The master should
supply a STOP condition to be consistent with the bus protocol.
After setting the WEL and/or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write operation.
14
FN8206.1
January 3, 2006