ISL62881_14 Datasheet, PDF (3/35 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs

ISL62881, ISL62881B
diode connected from the VCCP pin to the BOOT pin, each time
the PHASE pin drops below VCCP minus the voltage dropped
across the internal boot diode.
UGATE
Output of the high-side MOSFET gate driver. Connect the UGATE
pin to the gate of the high-side MOSFET.
PHASE
Current return path for the high-side MOSFET gate driver. Connect
the PHASE pin to the node consisting of the high-side MOSFET
source, the low-side MOSFET drain and the output inductor.
VSSP
Current return path for the low-side MOSFET gate driver. Connect
the VSSP pin to the source of the low-side MOSFET through a low
impedance path, preferably in parallel with the trace connecting
the LGATE pin to the gate of the low-side MOSFET.
LGATE (for ISL62881)
Output of the low-side MOSFET gate driver. Connect the LGATE
pin to the gate of the low-side MOSFET.
LGATEa (for ISL62881B)
Output of the low-side MOSFET gate driver that is always active.
Connect the LGATEa pin to the gate of the low-side MOSFET that
is active all the time.
LGATEb (For ISL62881B)
Another output of the low-side MOSFET gate driver. This gate
driver will be pulled low when the DPRSLPVR pin logic is high.
Connect the LGATEb pin to the gate of the low-side MOSFET that
is idle in deeper sleep mode.
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to
the VCCP pin. Decouple with at least 1µF of an MLCC capacitor to
VSSP1 and VSSP2 pins respectively.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
VR_ON
Voltage regulator enable input. A high level logic signal on this
pin enables the regulator.
DPRSLPVR
A high level logic signal on this pin puts the ISL62881 in 1-phase
diode emulation mode. If R_BIAS = 47kΩ (GPU VR application), this
pin also controls V_core slew rate. V_core slews at 5mV/µs for
DPRSLPVR = 0 and 10mV/µs for DPRSLPVR = 1. If R_BIAS = 147kΩ
(CPU VR application), this pin doesn’t control V_core slew rate.
3
FN6924.3
June 16, 2011