ISL62881_14 Datasheet, PDF (19/35 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs

ISL62881, ISL62881B
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC
network and the R_sum resistors form a voltage divider, V_cn is
always a fraction of the inductor DCR voltage. It is recommended
to have a higher ratio of V_cn to the inductor DCR voltage, so the
droop circuit has higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R_sum = 3.65kΩ, R_p = 11kΩ, R_ntcs = 2.61kΩ
and R_ntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.
V_Cn(s) also needs to represent real-time I_o(s) for the controller to
achieve good transient response. Transfer function A_cs(s) has a
pole ω_sns and a zero ω_L. One needs to match ω_L and ω_sns so
A_cs(s) is unity gain at all frequencies. By forcing ω_L equal to ω_sns
and solving for the solution, Equation 12 gives C_n value.
C_n = --_R--------_n------_t----_c------_n------_e------_t-------_{×---------R}----^L----_s------_u------_m----------_×----_D-----_C----_R--
R_ntcnet + R_sum
(EQ. 12)
i_o
For example, given R_sum = 3.65kΩ, R_p = 11kΩ, R_ntcs = 2.61kΩ,
R_ntc = 10kΩ, DCR = 1.1mΩ and L = 0.45µH, Equation 12 gives
C_n = 0.18µF.
Assuming the compensator design is correct, Figure 14 shows
the expected load transient response waveforms if C_n is correctly
selected. When the load current I_core has a square change, the
output voltage V_core also has a square response.
If C_n value is too large or too small, V_Cn(s) will not accurately
represent real-time I_o(s) and will worsen the transient response.
Figure 15 shows the load transient response when C_n is too
small. V_core will sag excessively upon load insertion and may
create a system failure. Figure 16 shows the transient response
when C_n is too large. V_core is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
i_O
i_L
V_O
RING
BACK
FIGURE 17. OUTPUT VOLTAGE RING BACK PROBLEM
ISUM+
V_o
FIGURE 14. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
i_o
Rntcs
Rp
Rntc
Cn.1
Rn
OPTIONAL
+
Cn.2 Vcn
-
Ri ^ISUM-
Rip ^Cip
V_o
FIGURE 15. LOAD TRANSIENT RESPONSE WHEN C_n IS TOO SMALL
i_o
V_o
FIGURE 16. LOAD TRANSIENT RESPONSE WHEN C_n IS TOO LARGE
OPTIONAL
FIGURE 18. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Figure 17 shows the output voltage ring back problem during
load transient response. The load current i_o has a fast step
change, but the inductor current i_L cannot accurately follow.
Instead, i_L responds in first order system fashion due to the
nature of current loop. The ESR and ESL effect of the output
capacitors makes the output voltage V_o dip quickly upon load
current change. However, the controller regulates V_o according to
the droop current i_droop, which is a real-time representation of i_L;
therefore it pulls V_o back to the level dictated by i_L, causing the
ring back problem. This phenomenon is not observed when the
output capacitors have very low ESR and ESL, such as all ceramic
capacitors.
19
FN6924.3
June 16, 2011