ISL12020M Datasheet, PDF (3/32 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12020M
Table of Contents
Block Diagram .................................................. 2
Pin Descriptions ............................................... 4
Absolute Maximum Ratings .............................. 5
Electrical Specifications .....................................6
SDA vs SCL Timing............................................ 8
Symbol Table .................................................... 8
Typical Performance Curves ............................. 8
General Description ........................................ 10
Functional Description.................................... 10
Power Control Operation ................................. 10
Normal Mode (V_DD) to Battery-Backup
Mode (V_BAT) ................................................ 10
Battery-Backup Mode (V_BAT) to Normal
Mode (V_DD) ................................................. 10
Power Failure Detection .................................. 11
Brownout Detection ........................................ 11
Battery Level Monitor...................................... 11
Real Time Clock Operation.............................. 11
Single Event and Interrupt .............................. 11
Frequency Output Mode .................................. 12
General Purpose User SRAM ............................ 12
I²C Serial Interface ........................................ 12
Oscillator Compensation.................................. 12
Register Descriptions ..................................... 12
Real Time Clock Registers .............................. 14
Addresses [00h to 06h]................................... 14
Control and Status Registers (CSR) ................ 14
Addresses [07h to 0Fh]................................... 14
Status Register (SR)....................................... 14
Interrupt Control Register (INT) ...................... 16
Initial AT and DT setting Register (ITRO) .......... 17
ALPHA Register (ALPHA)................................. 19
BETA Register (BETA) .................................... 19
Final Analog Trimming Register (FATR)............. 20
Final Digital Trimming Register (FDTR) ............. 21
ALARM Registers (10h to 15h)......................... 21
Time Stamp VDD to Battery Registers
(TSV2B) ..................................................... 22
Time Stamp Battery to VDD Registers
(TSB2V) ..................................................... 22
DST Control Registers (DSTCR) ....................... 22
TEMP Registers (TEMP)................................... 24
NPPM Registers (NPPM) .................................. 24
XT0 Registers (XT0)....................................... 24
ALPHA Hot Register (ALPHAH) ......................... 25
User Registers (Accessed by Using Slave
Address 1010111x) .................................. 25
Addresses [00h to 7Fh] ................................. 25
I²C Serial Interface ........................................ 25
Protocol Conventions ..................................... 25
Device Addressing.......................................... 26
Write Operation ............................................. 27
Read Operation .............................................. 27
Application Section ........................................ 27
Battery-Backup Details................................... 27
Layout Considerations .................................... 28
Measuring Oscillator Accuracy ......................... 28
Temperature Compensation Operation.............. 29
Daylight Savings Time (DST) Example.............. 29
Revision History ............................................. 30
Products......................................................... 31
3
FN6667.4
February 11, 2010