ISL12020M Datasheet, PDF(16/32 Page) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

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ISL12020M Datasheet, PDF (16/32 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

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ISL12020M

Interrupt Control Register (INT)

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

ADDR 7

3210

08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0

AUTOMATIC RESET BIT (ARST)

This bit enables/disables the automatic reset of the ALM,

LVDD, LBAT85, and LBAT75 status bits only. When ARST

bit is set to â1â, these status bits are reset to â0â after a

valid read of the respective status register (with a valid

STOP condition). When the ARST is cleared to â0â, the

user must manually reset the ALM, LVDD, LBAT85, and

LBAT75 bits.

WRITE RTC ENABLE BIT (WRTC)

The WRTC bit enables or disables write capability into the

RTC Timing Registers. The factory default setting of this

bit is â0â. Upon initialization or power-up, the WRTC must

be set to â1â to enable the RTC. Upon the completion of a

valid write (STOP), the RTC starts counting. The RTC

internal 1Hz signal is synchronized to the STOP condition

during a valid write cycle.

INTERRUPT/ALARM MODE BIT (IM)

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to â1â, the alarm will

operate in the interrupt mode, where an active low pulse

width of 250ms will appear at the IRQ/FOUT pin when

the RTC is triggered by the alarm, as defined by the

alarm registers (0Ch to 11h). When the IM bit is cleared

to â0â, the alarm will operate in standard mode, where

the IRQ/FOUT pin will be set low until the ALM status bit

is cleared to â0â.

TABLE 4.

IM BIT

INTERRUPT/ALARM FREQUENCY

Single Time Event Set By Alarm

Repetitive/Recurring Time Event Set By

Alarm

FREQUENCY OUTPUT AND INTERRUPT BIT

(FOBATB)

This bit enables/disables the IRQ/FOUT pin during

battery-backup mode (i.e. VBAT power source active).

When the FOBATB is set to â1â, the IRQ/FOUT pin is

disabled during battery-backup mode. This means that

both the frequency output and alarm output functions

are disabled. When the FOBATB is cleared to â0â, the

IRQ/FOUT pin is enabled during battery-backup mode.

Note that the open drain IRQ/FOUT pin will need a

pull-up to the battery voltage to operate in

battery-backup mode.

FREQUENCY OUT CONTROL BITS (FO<3:0>)

These bits enable/disable the frequency output function

and select the output frequency at the IRQ/FOUT pin.

See Table 5 for frequency selection. Default for the

ISL12020M is FO<3:0> = 1h, or 32.768kHz output

(FOUT is ON). When the frequency mode is enabled, it

will override the alarm mode at the IRQ/FOUT pin.

TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN

FREQUENCY, UNIT

FOUT

FO3

FO2

FO1

FO0

32768

4096

1024

1/2

1/4

1/8

1/16

1/32

POWER SUPPLY CONTROL REGISTER (PWR_VDD)

Clear Time Stamp Bit (CLRTS)

ADDR 7 6 5 4 3

09h

CLRTS 0 0 0 0 VDDTrip2 VDDTrip1 VDDTrip0

This bit clears Time Stamp VDD to Battery (TSV2B) and

Time Stamp Battery to VDD Registers (TSB2V). The

default setting is 0 (CLRTS = 0) and the Enabled setting

is 1 (CLRTS = 1).

VDD Brownout Trip Voltage BITS (VDDTrip<2:0>)

These bits set the trip level for the VDD alarm, indicating

that VDD has dropped below a preset level. In this event,

the LVDD bit in the Status Register is set to â1â. See

Table 6.

TABLE 6. VDD TRIP LEVELS

VDDTrip2

VDDTrip1

VDDTrip0

TRIP

VOLTAGE

(V)

2.295

2.550

2.805

3.060

4.250

4.675

FN6667.4

February 11, 2010

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