ISL12020M Datasheet, PDF (18/32 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12020M
AGING AND INITIAL ANALOG TRIMMING BITS
(IATR0<5:0>)
The Initial Analog Trimming Register allows +32ppm to
-31ppm adjustment in 1ppm/bit increments. This
enables fine frequency adjustment for trimming initial
crystal accuracy error or to correct for aging drift.
The ISL12020M has a preset Initial Analog Trimming
value corresponding to the crystal in the module. This
value is recalled on initial power-up and should
never be changed for best temperature
compensation performance, although the user
may change this preset value to adjust for aging
or board mounting changes if so desired.
The IATR0 register should only be changed while the TSE
(Temp Sense Enable) bit is “0”.
TABLE 11. INITIAL AT AND DT SETTING REGISTER
ADDR 7
6
5
4
3
21
0
0Bh IDTR IDTR IATR IATR IATR IATR IATR IATR
01 00 05 04 03 02 01 00
Note that setting the IATR to the lowest settings
(-31ppm) with the default 32kHz output can cause the
oscillator frequency to become unstable on power-up.
The lowest settings for IATR should be avoided to insure
oscillator frequency integrity.
IATR05
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IATR04
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
TABLE 12. IATRO TRIMMING RANGE
IATR03
IATR02
IATR01
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
IATR00
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TRIMMING RANGE
+32
+31
+30
+29
+28
+27
+26
+25
+24
+23
+22
+21
+20
+19
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
-1
-2
-3
-4
-5
-6
-7
18
FN6667.4
February 11, 2010