ISL6334B Datasheet, PDF (29/30 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Phase Dropping, Droop Disabled and Load Current Monitoring Features

ISL6334B, ISL6334C
0.3 _{IL(P-P) = 0}
I_L(P-P) = 0.25 I_O
0.2
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
0.6
0.4
0.2
I_L(P-P) = 0
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
MULTIPHASE RMS IMPROVEMENT
Figure 21 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a 2-phase
converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of I_L(P-P) to I_O of 0.5. The
single phase converter would require 17.3A_RMS current
capacity while the two-phase converter would only require
10.9A_RMS. The advantages become even more pronounced
when output current is increased and additional phases are
added to keep the component cost down relative to the
single phase approach.
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that space between
the components is minimized while creating the PHASE
plane. Place the Intersil MOSFET driver IC as close as
possible to the MOSFETs they control to reduce the parasitic
impedances due to trace length between critical driver input
and output signals. If possible, duplicate the same placement
of these components for each phase.
Next, place the input and output capacitors. Position one high-
frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to the
upper MOSFET drains as dictated by the component size and
dimensions. Long distances between input capacitors and
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output
capacitors between the inductors and the load, while keeping
them in close proximity to the microprocessor socket.
Voltage-Regulator (VR) Design Materials
The tolerance band calculation (TOB) worksheets for VR
output regulation and IMON have been developed using the
Root-Sum-Squared (RSS) method with 3 sigma distribution
point of the related components and parameters. Note that
the “Electrical Specifications” table beginning on page 8
specifies no less than 6 sigma distribution point, not suitable
for RSS TOB calculation. Intersil also developed a set of
worksheets to support VR design and layout. Contact
Intersil’s local office or field support for the latest available
information.
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FN6689.2
August 31, 2010