ISL6334B Datasheet, PDF (14/30 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Phase Dropping, Droop Disabled and Load Current Monitoring Features

ISL6334B, ISL6334C
operation is selected. In addition, tie PSI# to GND to
configure for single or 2-phase operation with diode
emulation on remaining channel(s), Channel 1 or Channels
1 and 3.
When PSI# is asserted low, it indicates the low power mode
operation of the processor. While in PSI# state, the controller
reduces the number of active phases according to the logic in
Table 1, improving light load efficiency. SS and FS pins are
used to program the controller in operation of non-coupled,
2-phase coupled, or (n-x)-Phase coupled inductors. Different
cases yield different PWM output behaviors on both dropped
phase(s) and remained phase(s) as PSI# is asserted and
de-asserted. A high PSI# input signal pulls the controller back
to normal CCM PWM operation to sustain an immediate heavy
transient load and high efficiency. Note that “n-x” means n-x
phases coupled and x phase(s) are uncoupled.
TABLE 1. PSI# OPERATION DECODING
PSI# FS SS
Non CI or (n-1) CI Drops to 1-phase
0
0
0
Non CI or (n-2) CI Drops to 2-phase
0
0
1
2-phase CI Drops to 1-phase
0
1
0
2-phase CI Drops to 2-phase
0
1
1
Normal CCM PWM Mode
1
x
x
Prior to VR_RDY going high (end of soft-start), the low power
mode operation (PSI# low) is disabled. In addition, a low on
H_CPURST_N disables PSI# mode, and low power mode is
not enabled until approximately 45ms (see “Electrical
Specifications” table on page 9 for expected timing range) after
H_CPURST_N returns to a logic high state. The low and high
thresholds on H_CPURST_N are approximately 0.4V and 0.8V,
as specified in the “Electrical Specifications” table on page 9. A
logic low can be obtained by pulling this pin to ground with a
suitable small signal device, while a logic high can be obtained
by leaving the pin open or connecting to processor VTT (~1.1V)
via a suitable pull-up. If the PSI# lockout is not desired at any
time during the operation of the IC, then H_CPURST_N should
be connected to VCC. This unique function of ISL6334B,
ISL6334C eliminates the required external circuitry for proper
PSI# operation of Intel’s Eaglelake chipset platforms, reducing
cost and PCB space. This function can be permanently
disabled, making the ISL6334B and ISL6334C compatible with
ISL6334 and ISL6334A, for other platform implementations.
The dropped PWM is forced low for 200ns (uncoupled case)
or until falling edge of coupled PWM (coupled case) then
pulled to VCC/2, while the remained PWM(s) sends out a
special 3-level PWM protocol that the dedicated VR11.1
drivers can decode and then enter diode emulation mode
with gate drive voltage optimization.
The ISL6334C only generates 2-level normal CCM PWM
except for faults. No dedicated VR11.1 driver is required.
See “Controller and Driver Recommendation” on page 3.
While the controller is operational (VCC above POR,
EN_VTT and EN_PWR are both high, valid VID inputs), it
can pull the PWM pins to ~40% of VCC (~2V for 5V VCC
bias) during various stages, such as soft-start delay, phase
shedding operation, or fault conditions (OC or OV events).
The matching driver's internal PWM resistor divider can
further raise the PWM potential, but not lower it below the
level set by the controller IC. Therefore, the controller's
PWM outputs are directly compatible with Intersil drivers that
require 5V PWM signal amplitudes. Drivers requiring 3.3V
PWM signal amplitudes are generally incompatible.
Switching Frequency
Switching frequency is determined by the selection of the
frequency-setting resistor, R_T, which is connected from FS
pin to GND or VCC. Equation 3 and Figure 3 are provided to
assist in selecting the correct resistor value.
R_T
=
2----.--5---X-----1---0----¹_---⁰_-
F_SW
(EQ. 3)
where F_SW is the switching frequency of each phase.
250
200
150
100
50
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
SWITCHING FREQUENCY (Hz)
FIGURE 3. SWITCHING FREQUENCY vs RT
Current Sensing
The ISL6334B, ISL6334C senses current continuously for
fast response. The ISL6334B, ISL6334C supports inductor
DCR sensing, or resistive sensing techniques. The
associated channel current sense amplifier uses the ISEN
inputs to reproduce a signal proportional to the inductor
current, I_L. The sense current, I_SEN, is proportional to the
inductor current. The sensed current is used for current
balance, load-line regulation, and overcurrent protection.
The internal circuitry, shown in Figures 4 and 5, represents
one channel of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM2, PWM3 and
PWM4 pins, as described in “PWM and PSI# Operation” on
page 13. The input bias current of the current sensing
amplifier is typically 60nA; less than 5kΩ input impedance is
preferred to minimized the offset error.
14
FN6689.2
August 31, 2010