ISL6334B Datasheet, PDF (28/30 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Phase Dropping, Droop Disabled and Load Current Monitoring Features

ISL6334B, ISL6334C
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV_MAX. This places an upper limit on inductance.
Equation 37 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 38
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
L
≤
2 ⋅ N ⋅ C ⋅ V_O
---------------------------------
(ΔI)²
ΔV_MAX – ΔI ⋅ ESR
(EQ. 37)
L ≤ -1---.--2---5-----^â‹---N------^â‹---C--
(ΔI)²
ΔV_MAX – ΔI ⋅ ESR
⎝⎛^{VIN – VO}⎠⎞
(EQ. 38)
Switching Frequency Selection
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 25, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 27. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
0.3
0.2
0.1
I_L(P-P) = 0
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVERTER
0.3
I_L(P-P) = 0
I_L(P-P) = 0.25 I_O
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 3-PHASE CONVERTER
For a 2-phase design, use Figure 18 to determine the input
capacitor RMS current requirement given the duty cycle,
maximum sustained output current (I_O), and the ratio of the
per-phase peak-to-peak inductor current (I_L(P-P)) to I_O.
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25x greater than the
maximum input voltage.
Figures 19 and 20 provide the same input RMS current
information for 3- and 4-phase designs respectively. Use the
same approach to selecting the bulk capacitor type and
number as previously described.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. The result from the high
current slew rates produced by the upper MOSFETs turn on
and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitic impedances and maximize suppression.
28
FN6689.2
August 31, 2010