ISL6334B Datasheet, PDF (27/30 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Phase Dropping, Droop Disabled and Load Current Monitoring Features

ISL6334B, ISL6334C
The feedback resistor, R_FB, has already been chosen as
outlined in “Load-Line Regulation Resistor” on page 26.
Select a target bandwidth for the compensated system, f₀.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
Case 1:
---------1----------
2π LC
>
f₀
R_C
=
R_F
B
2----π_{----f--0---V-----P------P--------L----C---}
0.75 V _{I N}
C_C
=
--------0---.--7---5----V----^I--^N---------
2πV_PPR_FBf₀
Case 2:
---------1----------
2π LC
≤
f₀
<
2----π^----C-----(^{-1-E-----S----R-----})
R_C
=
R_F
B
V-----_P------P----(_--2----π_----)_--²_-----f--0--²_----L---C---
0.75 V_IN
C_C
=
--------------------0----.-7----5---V-----^I--^N---------------------
(2π)² f₀₂ V_PPR_FB LC
(EQ. 34)
Case 3:
f₀ > _2----π----C-----₍-1-E-----S----R-----₎
R_C = R_{FB 0----.--7-2--5-}^π----V-f--⁰-_I--_N^V----P-₍--E-^---^P--S--L--R-----₎
C_C
=
-0---.--7---5----V----^I--^N----⁽--E-----S----R-----⁾-------C---
2πV_PPR_FBf₀ L
In Equation 34, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_PP is the sawtooth
amplitude described in the “Electrical Specifications” table
beginning on page 8.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator. Keep a position
available for C₂, and be prepared to install a high-frequency
capacitor of between 10pF and 100pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 34
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 34 unless some performance issue is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI;
the load-current slew rate, di/dt; and the maximum allowable
output-voltage deviation under transient loading, ΔV_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL
and ESR so that the total output-voltage deviation is less than
the allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount, as shown in Equation 35:
ΔV ≈ (ESL) -d---i + (ESR) ΔI
dt
(EQ. 35)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 12 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to I_C,PP (ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, V_PP(MAX), determines the lower limit on the
inductance, as shown in Equation 36.
L
≥ ESR ⋅
⎛
⎝
V_IN
–
N
V_O
⎞
U T_⎠
⋅
V_OUT
------f--_S-----_â‹---V----_I--_N-----_â‹---V----_P----_---_P---₍--_M-----_A----_X----₎-----
(EQ. 36)
27
FN6689.2
August 31, 2010