ISL6312A Datasheet, PDF (29/35 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10, VR11, and AMD Applications

ISL6312A
ΔV₂
ΔV₁
V_OUT
I_TRAN
ΔI
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
Loadline Regulation Resistor
For loadline regulation a copy of the internal average sense
current flows out of the FB pin across the loadline
regulation resistor, labeled R_FB in Figure 6. This resistor’s
value sets the desired loadline required for the application.
The desired loadline, R_LL, can be calculated by the following
equation where V_DROOP is the desired droop voltage at the
full load current I_FL.
R_LL
=
V-----_{D----R----O-----O----P--}
I_FL
(EQ. 39)
Based on the desired loadline, the loadline regulation
resistor, R_FB, can be calculated from Equation 40 or
Equation 41, depending on the R-C current sense circuitry
being employed. If a basic R-C sense circuit consisting of C₁
and R₁ is being used, use Equation 40. If a resistor divider
R-C sense circuit consisting of R₁, R₂, and C₁ is being used,
use Equation 41.
R_FB
=
-^R----^L---^L-----^â‹---^N------^â‹---³---⁰---⁰--
DCR
(EQ. 40)
R_FB
=
-^R----^L---^L-----^â‹---^N------^â‹---³---⁰---⁰-----^â‹---⁽---^R----¹-----+----^R-----²---⁾-
DCR ⋅ R₂
(EQ. 41)
In Equations 40 and 41, R_LL is the loadline resistance; N is
the number of active channels; DCR is the DCR of the
individual output inductors; and R₁ and R₂ are the current
sense R-C resistors.
IOUT Pin Resistor
A copy of the average sense current flows out of the IOUT
pin, and a resistor, R_IOUT, placed from this pin to ground can
be used to set the overcurrent protection trip level. Based on
the desired overcurrent trip threshold, I_OCP, the IOUT pin
resistor, R_IOUT, can be calculated from Equation 42 or
Equation 43, depending on the R-C current sense circuitry
being employed. If a basic R-C sense circuit consisting of C₁
and R₁ is being used, use Equation 42. If a resistor divider
R-C sense circuit consisting of R₁, R₂, and C₁ is being used,
use Equation 43.
R_IOUT = _D-----_C--⁶---_R-⁰---⁰--_â‹---^â‹_I--_O-^N---_C----_P--
I_OCP ≤ I_{OCP, min} (EQ. 42)
R_IOUT
=
-------⁶----⁰---⁰-----^â‹---^N---------
DCR ⋅ I_OCP
⋅
⎛
⎜
⎝
-^R----¹--_R--+---₂--^R-----²-_{⎠⎟⎞}
I_OCP > I_{OCP, min (EQ. 43)}
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed.
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
C₂ (OPTIONAL)
R_C ^CC
COMP
FB
ISL6312A
R_FB
VDIFF
FIGURE 20. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6312A CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f₀.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
29
FN9290.4
April 29, 2010