ISL6336CRZ-T Datasheet, PDF (28/31 Pages) Intersil Corporation – 6-Phase PWM Controller with Light Load Efficiency Enhancement and Current Monitoring

ISL6336, ISL6336A
R₁
=
R_F
B
----------C----⁽---E----S-----R-----⁾---------
LC – C(ESR)
C₁
=
-----L---C------^–-----C-----⁽--E-----S----R-----⁾
R_FB
C₂
=
------------------------0---.--7---5----V----^I--^N--------------------------
(2π)²f₀f_HF LCR_FBV_P-P
R_C
=
---V-----^P----^P----^⎝⎛--2----^π---^⎠⎞---²----f--⁰---f--^H----^F----L----C----R-----^F----^B----
0.75 V_{IN ⎝⎛}2πf_HF LC–1_⎠⎞
(EQ. 38)
C_C
=
---0---.--7---5----V----^I--^N-----^⎝⎛-2----^π----f--^H----^F--------L---C-----^–---1----^⎠⎞---
(2π)²f₀f_HF LCR_FBV_P-P
In Equation 38, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_PP is the peak-
to-peak sawtooth signal amplitude as described in the
“Electrical Specifications” table beginning on page 7.
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter necessarily limits the system
transient response. The output capacitor must supply or sink
load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ΔI; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ΔV_MAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount,
as shown in Equation 39:
ΔV
≈
(ESL)
⋅
-d---i
dt
+
(ESR)
⋅
ΔI
(EQ. 39)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 11 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to I_C,PP (ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, V_PP(MAX), determines the lower limit on the
inductance, as shown in Equation 40.
L
≥ (ESR) ⋅
⎝⎛ ^{V I N}
–
N
⋅
V_O
U
⎞
T_⎠
⋅
V_OUT
-------------------------------------------------------------------
f_S ⋅ V_IN ⋅ V_P-P(MAX)
(EQ. 40)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV_MAX. This places an upper limit on inductance.
Equation 41 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 42
addresses the leading edge. Normally, the trailing edge dictates
the selection of L because duty cycles are usually much less
than 50%. Nevertheless, both inequalities should be evaluated,
and L should be selected based on the lower of the two results.
In each equation, L is the per-channel inductance, C is the total
output capacitance, and N is the number of active channels.
L
≤
2 ⋅ N ⋅ C ⋅ V_O
---------------------------------
(ΔI)²
ΔV_MAX – (ΔI ⋅ (ESR))
(EQ. 41)
L
≤
1----.--2---5-----⋅_---N------⋅_---C--
(ΔI)²
ΔV_MAX – (ΔI ⋅ (ESR))
⋅
⎛
⎝
V_IN
–
V_{O⎠⎞}
(EQ. 42)
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 25, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
28
FN6504.1
May 28, 2009