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ISL6336CRZ-T Datasheet, PDF (15/31 Pages) Intersil Corporation – 6-Phase PWM Controller with Light Load Efficiency Enhancement and Current Monitoring
ISL6336, ISL6336A
.
ISL6336, ISL6336A
INTERNAL CIRCUIT
In
IL
L
RSENSE VOUT
COUT
RISEN(n)
CURRENT
SENSE
ISEN-(n)
+
-
ISEN+(n)
CT
ISEN
=
IL
-R----S-----E----N-----S----E---
RISEN
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
Channel-Current Balance
The sensed current In from each active channel are summed
together and divided by the number of active channels. The
resulting average current IAVG provides a measure of the
total load current. Channel current balance is achieved by
comparing the sensed current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel with Intersil’s patented
current-balance method.
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 6 assures that
the steady-state error in the output voltage is limited only to
the error in the reference voltage (output of the DAC) and
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6336, ISL6336A to include the combined tolerances
of each of these elements.
The output of the error amplifier, VCOMP, is compared to the
sawtooth waveforms to generate the PWM signals. The
PWM signals control the timing of the Intersil MOSFET
drivers and regulate the converter output to the specified
reference voltage. The internal and external circuitries which
control the voltage regulation are illustrated in Figure 6.
The ISL6336, ISL6336A incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
output, VDIFF, is connected to the inverting input of the error
amplifier through an external resistor.
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the 8-bit logic signal (VID)
into one of the discrete voltages shown in Table 3. Each VID
input has an internal 30µA minimum pull-up to VCC after
tD3. The pull-up current diminishes to zero above the logic
threshold (near 1V) to protect voltage-sensitive output
devices. External pull-up resistors can augment the pull-up
current sources in case the leakage into the driving device is
greater than 30µA.
EXTERNAL CIRCUIT
RC CC COMP
RREF
CREF
DAC
REF
RFB
+
VDROOP
-
FB
VDIFF
ISL6336, ISL6336A
INTERNAL CIRCUIT
+
-
VCOMP
ERROR AMPLIFIER
IAVG
VOUT+
VSEN
+
VOUT-
RGND
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
TABLE 3. VR11 VID 8-BIT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0 1.60000
0
0
0
0
0
0
1
1 1.59375
0
0
0
0
0
1
0
0 1.58750
0
0
0
0
0
1
0
1 1.58125
0
0
0
0
0
1
1
0 1.57500
0
0
0
0
0
1
1
1 1.56875
0
0
0
0
1
0
0
0 1.56250
0
0
0
0
1
0
0
1 1.55625
0
0
0
0
1
0
1
0 1.55000
0
0
0
0
1
0
1
1 1.54375
0
0
0
0
1
1
0
0 1.53750
15
FN6504.1
May 28, 2009