ISL6336CRZ-T Datasheet, PDF (19/31 Pages) Intersil Corporation – 6-Phase PWM Controller with Light Load Efficiency Enhancement and Current Monitoring

ISL6336, ISL6336A
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of the normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during the regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
In order to ensure a smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R_REF and C_REF, can be used. The selection of
R_REF is based on the desired offset voltage as detailed
above in “Output-Voltage Offset Programming” on page 18.
The selection of C_REF is based on the time duration for 1-bit
VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every t_VID, the relationship between the time constant
of R_REF and C_REF network and t_VID is given by Equation 13.
C_REF ⋅ R_REF = t_VID
(EQ. 13)
During dynamic VID transition and VID up steps, the
overcurrent trip point increases by 140% to avoid false
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If dynamic VID occurs
when PSI# is asserted, the controller will activate all phases
and complete the transition at which point the status of the
PSI# pin will control operation.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6336,
ISL6336A is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6336, ISL6336A is guaranteed. Hysteresis
between the rising and falling thresholds assure that once
enabled, the ISL6336, ISL6336A will not inadvertently
turn off unless the bias voltage drops substantially (see
“Electrical Specifications” table beginning on page 7).
2. The ISL6336, ISL6336A features an enable input
(EN_PWR) for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6336, ISL6336A in shutdown
until the voltage at EN_PWR rises above 0.875V. The
enable comparator has about 130mV of hysteresis to
prevent bounce. It is important that the driver ICs reach
their POR level before the ISL6336, ISL6336A becomes
enabled. The schematic in Figure 8 demonstrates
sequencing the ISL6336, ISL6336A with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of the VTT voltage regulator.
ISL6336, ISL6336A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
100kΩ
EN_PWR
9.1kΩ
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
0.875V
FIGURE 8. POWER SEQUENCING USING THRESHOLD
SENSITIVE ENABLE (EN) FUNCTION
When all conditions above are satisfied, ISL6336, ISL6336A
begins soft-start and ramps the output voltage to 1.1V first.
After remaining at 1.1V for some time, ISL6336, ISL6336A
reads the VID code at VID input pins. If the VID code is valid,
ISL6336, ISL6336A will regulate the output to the final VID
setting. If the VID code is an OFF code, ISL6336, ISL6336A
will shut down, and cycling VCC, EN_PWR or EN_VTT is
needed to restart.
Soft-Start
ISL6336, ISL6336A based VR has 4 periods during soft-start
as shown in Figure 9. After VCC, EN_VTT and EN_PWR
reach their POR/enable thresholds, The controller will have
fixed delay period t_D1. After this delay period, the VR will
begin first soft-start ramp until the output voltage reaches
1.1V Vboot voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed period t_D3. At the end of t_D3
period, ISL6336, ISL6336A reads the VID signals. If the VID
code is valid, ISL6336, ISL6336A will initiate the second
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FN6504.1
May 28, 2009