ISL6266AHRZ Datasheet, PDF (28/30 Pages) Intersil Corporation – Two-phase Core Controllers (Montevina, IMVP-6+)

ISL6266, ISL6266A
a mathematical calculation file available to the user. The
power stage parameters such as L and Cs are needed as
the input to calculate the compensation component values.
Attention must be paid to the input resistor to the FB pin. Too
high of a resistor will cause an error to the output voltage
regulation because of bias current flowing in the FB pin. It is
better to keep this resistor below 3kΩ when using this file.
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6266A by measuring
the voltages present on the ISEN pins and adjusting the duty
cycle of each phase until they match. R_L and C_L around
each inductor, or around each discrete current resistor, are
used to create a rather large time constant such that the
ISEN voltages have minimal ripple voltage and represent the
DC current flowing through each channel's inductor. For
optimum performance, R_L is chosen to be 10kΩ and C_L is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor most likely needs to be placed in parallel
with R_L to properly compensate the current balance circuit.
ISL6266A uses an RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL6266A forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly equal. Using DCR
current sensing as an example, two errors have to be added
to find the total current imbalance.
1. Mismatch of DCR: If the DCR has a 5% tolerance, the
resistors could mismatch by 10% worst case. If each
phase is carrying 20A, the phase currents mismatch by
20A*10% = 2A.
2. Mismatch of phase voltages/offset voltage of ISEN pins:
The phase voltages are within 2mV of each other by the
current balance circuit. The error current that results is
given by 2mV/DCR. If DCR = 1mΩ then the error is 2A.
In the previous example, the two errors add to 4A. For the
two phase DC/DC, the currents would be 22A in one phase
and 18A in the other phase. In the previous analysis, the
current balance can be calculated with 2A/20A = 10%. This
is the worst case calculation. For example, the actual
tolerance of two 10% DCRs is 10%*√(2) = 7%.
There are provisions to correct the current imbalance due to
layout or to purposely divert current to certain phase for
better thermal management. The Customer can put a
resistor in parallel with the current sensing capacitor on the
phase of interest in order to purposely increase the current in
that phase.
If the PC board trace resistance from the inductor to the
microprocessor are significantly different between two
phases, the current will not be balanced perfectly. Intersil
has a proprietary method to achieve the perfect current
sharing in cases of severely imbalanced layouts.
When choosing the current sense resistor, both the
tolerance of the resistance and the TCR are important. Also,
the current sense resistor’s combined tolerance at a wide
temperature range should be calculated.
Droop Using Discrete Resistor Sensing -
Static/Dynamic Mode of Operation
Figure 42 shows the equivalent circuit of a discrete current
sense approach. Figure 33 shows a more detailed
schematic of this approach. Droop is solved the same way
as the DCR sensing approach with a few slight
modifications.
First, because there is no NTC required for thermal
compensation, the R_n resistor network in the previous
section is not required. Second, because there is no time
constant matching required, the C_n component is not
matched to the L/DCR time constant. This component does
indeed provide noise immunity and therefore is populated
with a 39pF capacitor.
The R_S values in the previous section, R_S = 1.5k_1%, are
sufficient for this approach.
Now the input to the droop amplifier is essentially the
V_rsense voltage. This voltage is given by Equation 34.
Vrsense_EQV
=
R_{-----s---e---n----s---e-}
2
•
I_OUT
(EQ. 34)
The gain of the droop amplifier, K_droopamp, must be adjusted
for the ratio of the R_sense to droop impedance, R_droop by
using Equation 35.
K_droopamp
=
-------^R-----^d---^r--^o----^o---^p--------
(R_sense ⁄ 2)
(EQ. 35)
Solving for the R_drp2 value, R_droop = 0.0021(V/A) as per the
Intel IMVP-6+ specification, R_sense = 0.001Ω and R_drp1 = 1kΩ,
Equation 36 is obtained:
R_drp2 = (K_droopamp – 1) • R_drp1= 3.2kΩ
(EQ. 36)
Because these values are extremely sensitive to layout,
some tweaking may be required to adjust the full load droop.
This is fairly easy and can be accomplished by allowing the
system to achieve thermal equilibrium at full load, and then
adjusting R_drp2 to obtain the desired droop value.
Fault Protection - Overcurrent Fault Setting
As previously described, the overcurrent protection of the
ISL6266A is related to the droop voltage. Previously the
droop voltage was calculated as I_Load*R_droop, where R_droop
is the load line slope specified as 0.0021 (V/A) in the Intel
IMVP-6+ specification. Knowing this relationship, the
overcurrent protection threshold can be programmed as an
equivalent droop voltage droop. Knowing the voltage droop
level allows the user to program the appropriate drop across
the R_OC resistor. This voltage drop will be referred to as
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FN6398.3
June 14, 2010