ISL6266AHRZ Datasheet, PDF (22/30 Pages) Intersil Corporation – Two-phase Core Controllers (Montevina, IMVP-6+)

ISL6266, ISL6266A
volt-second balance. The ISL6266 continues to turn on the
lower MOSFET for the inactive channel to deplete the induced
field with minimum power loss.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6266A uses two slew rates for various modes of
operation. The first is a slow slew rate used to reduce in-rush
current during start-up. It is also used to reduce audible noise
when entering or exiting Deeper Sleep Mode. A faster slew rate
is used to exit out of Deeper Sleep and to enhance system
performance by achieving active mode regulation more quickly.
Note that the SOFT capacitor current is bidirectional. The
current is flowing into the SOFT capacitor when the output
voltage is commanded to rise and out of the SOFT capacitor
when the output voltage is commanded to fall.
Figure 36 illustrates how the two slew rates are determined
by commanding one of two current sources into or out of the
SOFT pin. The capacitor from the SOFT pin to ground holds
the voltage commanded by the two current sources. The
voltage is fed into the non-inverting input of the error
amplifier and sets the regulated system voltage. Depending
on the state of the system (Start-Up or Active mode) and the
state of the DPRSLPVR pin, one of the two currents shown
in Figure 36 will be used to charge or discharge this
capacitor, thereby controlling the slew rate of the newly
commanded voltage. These currents can be found under
“SOFT-START CURRENT” on page 4 of the “Electrical
Specifications” table.
ISL6266, ISL6266A
I_SS
SOFT
C_SOFT
+
V_REF
I₂ ERROR
AMPLIFIER
+
FIGURE 36. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
The first current, labeled I_SS, is given in the “Electrical
Specifications” table on page 4 as 42µA. This current is used
during soft-start. The second current (I₂) sums with I_SS to
get the larger of the two currents, labeled I_GV in the
“Electrical Specifications” table on page 4. This total current
is typically 205µA with a minimum of 180µA.
The IMVP-6+ specification dictates the critical timing
associated with regulating the output voltage. The symbol,
SLEWRATE, as given in the IMVP-6+ specification will
determine the choice of the SOFT capacitor (C_SOFT) by
Equation 4.
C_SOFT
=
--------------^I--^G----^V---------------
SLEWRATE
(EQ. 4)
Using a SLEWRATE of 10mV/µs and the typical I_GV value
given in the “Electrical Specifications” table on page 4 of
205µA, C_SOFT is as shown in Equation 5.
C_SOFT = 205μA ⁄ (10mV ⁄ 1μs)
(EQ. 5)
A choice of 0.015µF would guarantee a SLEWRATE of
10mV/µs is met for the minimum I_GV value given in the
“Electrical Specifications” table on page 4. This choice of
C_SOFT will then control the start-up slewrate as well. One
should expect the output voltage to slew to the boot value of
1.2V at a rate given by Equation 6.
d_----V_---
dt
=
------^I--^S----^S-------
C_SOFT
=
0^----.^-40---1-1^---μ5^----Aμ^----F^--
=
2.8mV ⁄ μs
(EQ. 6)
Selecting RBIAS
To properly bias the ISL6266A, a reference current is
established by placing a 147kΩ, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate
10µA current source from which the OCSET reference
current can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Start-Up Operation - CLK_EN# and PGOOD
The ISL6266A provides a 3.3V logic output pin for
CLK_EN#. The 3V3 pin allows for a system 3.3V source to
be connected to separated circuitry inside the ISL6266A,
solely devoted to the CLK_EN# function. The output is a
3.3V CMOS signal with 4mA sourcing and sinking capability.
This implementation removes the need for an external
pull-up resistor on this pin, thereby removing a leakage path
from the 3.3V supply to ground when the logic state is low.
The lack of superfluous current leakage paths serves to
prolong battery life. For noise immunity, the 3.3V supply
should be decoupled to digital ground rather than to analog
ground.
As mentioned in “Theory of Operation” on page 18,
CLK_EN# is logic level high at start-up until approximately
43µs after the V_{CC_CORE} is in regulation at the Boot level.
Afterwards, CLK_EN# transitions low, triggering an internal
timer for the IMVP6_PWRGD signal. When the timer
reaches 6.8ms, IMVP-6_PWRGD will toggle high.
22
FN6398.3
June 14, 2010