ISL6266AHRZ Datasheet, PDF (20/30 Pages) Intersil Corporation – Two-phase Core Controllers (Montevina, IMVP-6+)

ISL6266, ISL6266A
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the active-
phase, and detects the idling-phase zero-current condition.
During transitions into automatic-DCM or forced-CCM mode,
the timing is carefully adjusted to eliminate output voltage
excursions. When a phase is added, the current balance
between phases is quickly restored.
When commanded into 1-phase CCM operation according
to Table 2, both MOSFETs of Phase 2 will be off. The
controller will thus eliminate switching losses associated with
the unneeded channel.
V_OUT AND V_SOFT
-2.5mV/µs
10mV/µs
DPRSLPVR
2.5mV/µs
VID#
FIGURE 35. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR'S EFFECT ON EXIT SLEW RATE
When commanded to single-phase DCM mode, both
MOSFETs associated with Phase 2 are off, and the
ISL6266A turns off the lower MOSFET of Channel 1
whenever the Channel 1 current decays to zero. As load is
further reduced, the Phase 1 channel switching frequency
decreases to maintain high efficiency. The operation of the
inactive for 1-phase DCM and 1-phase CCM described
previously refers to the ISL6266A only. See “ISL6266
Features” on page 21 for information on the ISL6266.
The ISL6266A can be configured to operate as a single
phase regulator using the same layout as a two phase
design to accommodate lower power CPUs. To accomplish
this, the designer must connect ISEN1 and ISEN2 to
VCC_PRM (reference AN1376 for signal names). Channel 2
components can be removed as well as current balance
circuitry. The ISL6266A will power-up and regulate in DCM
or CCM based on the state of PSI#, as outlined in Table 2.
The OCP threshold will also change based on the state of
PSI#, as outlined in “Protection” on page 20.
Dynamic Operation
Figure 35 shows that the ISL6266A responds to changes in
VID command voltage by slewing to new voltages with a
dV/dt set by the SOFT capacitor and by the state of
DPRSLPVR. With C_SOFT = 15nF and DPRSLPVR HIGH,
the output voltage will move at ±2.8mV/µs for large changes
in voltage. For DPRSLPVR LOW, the large signal dV/dt will
be ±10mV/µs. As the output voltage approaches the VID
command value, the dV/dt moderates to prevent overshoot.
Keeping DPRSLPVR HIGH for voltage transitions into and
out of Deeper Sleep will result in low dV/dt output voltage
changes with resulting minimized audio noise. For fastest
recovery from Deeper Sleep to Active mode, holding
DPRSLPVR LOW results in maximum dV/dt. Therefore, the
ISL6266A is IMVP-6+ compliant for DPRSTP# and
DPRSLPVR logic.
Intersil's R³ Technology™ has intrinsic voltage feedforward.
As a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6266A will transiently raise
the switching frequency so that response time is decreased
and current is shared by two channels.
Protection
The ISL6266A provides overcurrent, overvoltage,
undervoltage protection and over-temperature protection, as
shown in Table 3.
Overcurrent fault
Way-Overcurrent fault
Overvoltage fault (1.7V)
Overvoltage fault (+200mV)
Undervoltage fault
(-300mV)
Current imbalance fault
(7.5mV)
Over-temperature fault
(NTC <1.18V)
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6266, ISL6266A
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
120µs
PWM1, PWM2 three-state, PGOOD latched low VR_ON toggle or VDD toggle
<2µs
PWM1, PWM2 three-state, PGOOD latched low VR_ON toggle or VDD toggle
Immediately
Low-side MOSFET on until V_CORE <0.85V, then PWM VDD toggle
three-state, PGOOD latched low (0V to 1.7V always)
1ms
PWM1, PWM2 three-state, PGOOD latched low VR_ON toggle or VDD toggle
1ms
PWM1, PWM2 three-state, PGOOD latched low VR_ON toggle or VDD toggle
1ms
PWM1, PWM2 three-state, PGOOD latched low VR_ON toggle or VDD toggle
Immediately
VR_TT# goes low
N/A
20
FN6398.3
June 14, 2010