ISL6266AHRZ Datasheet, PDF (26/30 Pages) Intersil Corporation – Two-phase Core Controllers (Montevina, IMVP-6+)

ISL6266, ISL6266A
R_O is typically 1Ω to 10Ω. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. R_S is determined
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the outputs of
each of these R_S resistors are tied together to create the
VSUM voltage node. With both the outputs of R_O and R_S
tied together, the simplified model for the droop circuit can
be derived. This is presented in Figure 40.
Figure 40 shows the simplified model of the droop circuitry.
Essentially, one resistor can replace the R_O resistors of each
phase and one R_S resistor can replace the R_S resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by
Equation 19:
V_{DCR_EQU}
=
-^I-^O-----^U----^T-----^•----^D-----^C-----^R--
2
(EQ. 19)
For the convenience of analysis, the NTC network
comprised of R_ntc, R_series and R_par, given in Figure 37, is
labeled as a single resistor R_N in Figure 40.
The first step in droop load line compensation is to adjust
R_N, RO_EQV and RS_EQV such that sufficient droop voltage
exists even at light loads between the VSUM and VO' nodes.
As a rule of thumb, we start with the voltage drop across the
R_N network, Vn, to be 0.5x to 0.8x V_{DCR_EQU}. This ratio
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
The resultant NTC network resistor value is dependent on
the temperature and given by Equation 20.
R_n(T)
=
-⁽--^R-----^s---^e---^r--ⁱ--^e---^s----+-----^R-----ⁿ---^t--^c---⁾---^•-----^R----^p---^a----^r
R_series + R_ntc + R_par
(EQ. 20)
For simplicity, the gain of Vn to the V_{DCR_EQU} is defined by
G1, also dependent on the temperature of the NTC
thermistor.
G₁(T)
Δ
=
--------------^R-----ⁿ---⁽---^T----⁾--------------
R_n(T) + RS_EQV
(EQ. 21)
DCR(T) = DCR_25°C • (1 + 0.00393*(T-25))
(EQ. 22)
Therefore, the output of the droop amplifier divided by the
total load current can be expressed as shown in
Equation 23, where R_droop is the realized load line slope
and 0.00393 is the temperature coefficient of the copper.
R_droop
=
G₁
(T
)
•
-^D----^C-----^R-----²---⁵-
2
•
(1
+
0.00393 *(T-25) )
•
k_dr
oo
p
am
p
(EQ. 23)
How to achieve the droop value independent of the inductor
temperature is expressed by Equation 24.
G₁(T) • (1 + 0.00393*(T-25)) ≅ G_{1t arget}
(EQ. 24)
The non-inverting droop amplifier circuit has the gain
K_droopamp expressed as Equation 25:
k_droopamp
=
1
+
R_{-----d---r---p---2-}
R_drp1
(EQ. 25)
G_1target is the desired gain of Vn over I_OUT • DCR/2.
Therefore, the temperature characteristics of gain of Vn is
described by Equation 26.
G₁(T)
=
-----------------^G----¹----^t--^a---^r--^g---^e---^t----------------
(1 + 0.00393*(T-25))
(EQ. 26)
For the G_1target = 0.76:
R_ntc = 10kΩ with b = 4300,
R_series = 2610Ω, and
R_par = 11kΩ
RS_EQV = 1825Ω generates a desired G1, close to the
feature specified in Equation 26.
The actual G1 at +25°C is 0.769. A design file is available to
generate the proper values of R_ntc, R_series, R_par, and
RS_EQV for values of the NTC thermistor and G1 that differ
from the example provided here.
The individual resistors from each phase to the VSUM node,
labeled R_S1 and R_S2 in Figure 37, are then given by
Equation 27.
Rs = 2 • RS_EQV
(EQ. 27)
So, R_S = 3650Ω. Once we know the attenuation of the R_S
and R_N network, we can then determine the droop amplifier
gain required to achieve the load line. Setting
R_drp1 = 1k_1%, then R_drp2 can be found using Equation 28.
R_drp2
=
⎛
⎝
----------²-----^•----^R-----^d---^r--^o----^o---^p-----------
DCR • G1(25°C)
–
1_⎠⎞
• R_drp1
(EQ. 28)
Droop Impedance (R_droop) = 0.0021 (V/A) as per the Intel
IMVP-6+ specification. Using DCR = 0.0008Ω typical for a
0.36µH inductor, R_drp1 = 1kΩ and the attenuation gain
(G1) = 0.77, R_drp2 is then given by Equation 29:
R_drp2
=
⎛
⎝
0^----.^--02^---0^--•-0^---R-8^---d-•^---r--0^o---.^o--7^--p-6^---9^--
–
1_⎠⎞
• 1kΩ ≈ 5.82kΩ
(EQ. 29)
Note, we choose to ignore the R_O resistors because they do
not add significant error.
These designed values in R_n network are very sensitive to
the layout and coupling factor of the NTC to the inductor. As
only one NTC is required in this application, this NTC should
be placed as close to the Channel 1 inductor as possible and
PCB traces sensing the inductor voltage should route
directly to the inductor pads.
Due to layout parasitics, small adjustments may be
necessary to accurately achieve the full load droop voltage.
This can be easily accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
R_drp2 to obtain the appropriate load line slope.
26
FN6398.3
June 14, 2010