ISL6327 Datasheet, PDF (27/30 Pages) Intersil Corporation – Enhanced 6-Phase PWM Controller with 8-Bit VID Code and Differential Inductor DCR or Resistor Current Sensing

ISL6327
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount:
ΔV ≈ (ESL) -d---i + (ESR) ΔI
dt
(EQ. 37)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to I_C,PP (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
V_PP(MAX), determines the lower limit on the inductance.
L
≥
(ESR)
⎛
⎝
V_I
N
–
N
V_O
U
⎞
T_⎠
V_O
U
T
-----------------------------------------------------------
f_S V_{I N} V_{P P( M A X )}
(EQ. 38)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV_MAX. This places an upper limit on inductance.
Equation 39 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 40
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
L ≤ -2---N-----C-----V----^O---
(ΔI)²
ΔV_MAX – ΔI(ESR)
(EQ. 39)
Input Supply Voltage Selection
The VCC input of the ISL6327 can be connected either
directly to a +5V supply or through a current limiting resistor
to a +12V supply. An integrated 5.8V shunt regulator
maintains the voltage on the VCC pin when a +12V supply is
used. A 300Ω resistor is suggested for limiting the current
into the VCC pin to a worst-case maximum of approximately
25mA.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in MOSFETs, and they establish the upper limit for
the switching frequency. The lower limit is established by the
requirement for fast transient response and small output-
voltage ripple as outlined in Output Filter Design. Choose the
lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, R_T (see the figures labelled
Typical Application on pages 4 and 5). Equation 3 is
provided to assist in selecting the correct value for R_T.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs that is related to duty cycle and the number of
active phases.
0.3
0.2
0.1
I_L,PP = 0
I_L,PP = 0.5 I_O
I_L,PP = 0.75 I_O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVERTER
L ≤ -⁽--1---.--2---5----⁾---N----C---
(ΔI)²
ΔV_MAX – ΔI(ESR)
⎛
⎝
V_IN
–
V_{O⎠⎞}
(EQ. 40)
27
FN9276.2
December 20, 2006