ISL6327 Datasheet, PDF (19/30 Pages) Intersil Corporation – Enhanced 6-Phase PWM Controller with 8-Bit VID Code and Differential Inductor DCR or Resistor Current Sensing

ISL6327
When all conditions above are satisfied, ISL6327 begins the
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6327 reads the VID
code at VID input pins. If the VID code is valid, ISL6327 will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6327 will shut down, and cycling VCC,
EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6327 based VR has 4 periods during soft-start as shown
in Figure 8. After VCC, EN_VTT and EN_PWR reach their
POR/enable thresholds, The controller will have fixed delay
period TD1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V Vboot
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period TD3. At the end of TD3 period,
ISL6327 reads the VID signals. If the VID code is valid,
ISL6327 will initiate the second soft-start ramp until the
voltage reaches the VID voltage minus offset voltage.
VOUT, 500mV/DIV
TD1
TD2 TD3 TD4 TD5
EN_VTT
VR_RDY
500µs/DIV
FIGURE 8. SOFT-START WAVEFORMS
The soft-start time is the sum of the 4 periods as shown in
the following equation:
T_SS = TD1 + TD2 + TD3 + TD4
(EQ. 14)
TD1 is a fixed delay with the typical value as 1.36ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
During TD2 and TD4, ISL6327 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R_SS from SS pin to GND. The two
soft-start ramp times TD2 and TD4 can be calculated based
on the following equations:
TD2 = ^{1----.-1----x----R----S}----^S-- (μs)
6.25 x 25
(EQ. 15)
TD4
=
-⁽--V----^V----^I--^D-----^–-----1---.--1----⁾--x---R-----^S----^S--
6.25 x 25
(μs
)
(EQ. 16)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time TD2 will be 704µs and
the second soft-start ramp time TD4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay TD5. The
typical value for TD5 is 85µs.
Fault Monitoring and Protection
The ISL6327 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 9 outlines
the interaction between the fault monitors and the VR_RDY
signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period is completed and the output voltage
is within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and
a fix delay time,TD5. VR_RDY will be pulled low when an
undervoltage, overvoltage, or overcurrent condition is
detected, or the controller is disabled by a reset from
EN_PWR, EN_VTT, POR, or VID OFF-code.
VR_RDY
UV
50%
DAC
SOFT-START, FAULT
AND CONTROL LOGIC
-
OC
+
85µA
I_AVG
VDIFF
+
OV
-
VID + 0.175V
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
19
FN9276.2
December 20, 2006