ISL6327 Datasheet, PDF (18/30 Pages) Intersil Corporation – Enhanced 6-Phase PWM Controller with 8-Bit VID Code and Differential Inductor DCR or Resistor Current Sensing

ISL6327
FB
DYNAMIC
VID D/A
DAC
R_REF
E/A
REF
VCC
OR
GND
-
1.6V
+
+
0.4V
-
R_OFS
OFS
ISL6327
VCC
GND
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of the normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs during the regulator operation. The power management
solution is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner. Supervising
the safe output voltage transition within the DAC range of the
processor without discontinuity or disruption is a necessary
function of the core-voltage regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R_REF and C_REF, can be used. The selection of
R_REF is based on the desired offset voltage as detailed
above in Output-Voltage Offset Programming. The selection
of C_REF is based on the time duration for 1 bit VID change
and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T_VID, the relationship between the time constant of
R_REF and C_REF network and T_VID is given by Equation 13.
C_REF R_REF = T_VID
(EQ. 13)
Operation Initialization
Prior to converter initialization, proper conditions must exist on
the enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within
the proper window of operation, VR_RDY asserts logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6327 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6327 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6327 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications).
2. The ISL6327 features an enable input (EN_PWR) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6327 in shutdown until the voltage at EN_PWR rises
above 0.875V. The enable comparator has about 130mV
of hysteresis to prevent bounce. It is important that the
driver ICs reach their POR level before the ISL6327
becomes enabled. The schematic in Figure 7
demonstrates sequencing the ISL6327 with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
ISL6327 INTERNAL CIRCUIT EXTERNAL CIRCUIT
VCC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
10kΩ
EN_PWR
910Ω
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
0.875V
FIGURE 7. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
18
FN9276.2
December 20, 2006