ISL12022MR5421 Datasheet, PDF (26/29 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated 5ppm

ISL12022MR5421
“read” section. For a random read of the Control/Status
Registers, the slave byte must be “1101111x” in both
places.
1
1
0
1
11
1
R/
SLAVE
ADDRESS BYTE
A7 A6 A5 A4 A3 A2 A1 A0 WORD
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 18. SLAVE ADDRESS, WORD ADDRESS AND
DATA BYTES
Write Operation
A Write operation requires a START condition, followed by
a valid Identification Byte, a valid Address Byte, a Data
Byte, and a STOP condition. After each of the three
bytes, the ISL12022MR5421 responds with an ACK. At
this time, the I²C interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction,
followed by one or more Data Bytes (see Figure 20).
The master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit set to “0”, an Address Byte, a second START, and a
second Identification byte with the R/W bit set to “1”.
After each of the three bytes, the ISL12022MR5421
responds with an ACK. Then the ISL12022MR5421
transmits Data Bytes as long as the master responds
with an ACK during the SCL cycle following the eighth
bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last
bit of the last Data Byte (see Figure 20).
The Data Bytes are from the memory location indicated
by an internal pointer. This pointer’s initial value is
determined by the Address Byte in the Read operation
instruction, and increments by one during transmission
of each Data Byte. After reaching the memory location
2Fh, the pointer “rolls over” to 00h, and the device
continues to output data for each ACK received.
Application Section
Battery Backup Details
The ISL12022MR5421 has automatic switchover to
battery backup when the V_DD drops below the V_BAT
mode threshold. A wide variety of backup sources can be
used, including standard and rechargeable lithium,
supercapacitors, or regulated secondary sources. The
serial interface is disabled in battery backup, while the
oscillator and RTC registers are operational. The SRAM
register contents are powered to preserve their contents
as well.
The input voltage range for V_BAT is 1.8V to 5.5V, but
keep in mind the temperature compensation only
operates for V_BAT > 2.7V. Note that the device is not
guaranteed to operate with a V_BAT < 1.8V, so the battery
should be changed before discharging to that level. It is
strongly advised to monitor the low battery indicators in
the status registers and take action to replace discharged
batteries.
If a supercapacitor is used, it is possible that it may
discharge to below 1.8V during prolonged power-down.
Once powered up, the device may lose serial bus
communications until both V_DD and V_BAT are powered
down together. To avoid that situation, including
situations where a battery may discharge deeply, the
circuit in Figure 19 can be used.
V_DD = 2.7V
TO 5.5V
C_IN
0.1µF
ISL12022MR5421 J_BAT
VDD VBAT
C_BAT
0.1µF
D_BAT
BAT43W
+V^{BAT = 1.8V}
TO 3.2V
GND
FIGURE 19. SUGGESTED BATTERY BACKUP CIRCUIT
The diode, D_BAT will add a small drop to the battery
voltage but will protect the circuit should battery voltage
drop below 1.8V. The jumper is added as a safeguard
should the battery ever need to be disconnected from the
circuit.
The V_DD negative slew rate should be limited to below
the data sheet spec (10V/ms) otherwise battery
switchover can be delayed, resulting in SRAM contents
corruption and oscillator operation interruption.
Some applications will require separate supplies for the
RTC
may
V_DD and the
compromise
I²C
the
pull-ups. This is
operation of the
not
I²C
advised,
bus. For
as
it
applications that do require serial bus communication
with the RTC V_DD powered down, the SDA pin must be
pulled low during the time the RTC V_DD ramps down to
0V. Otherwise, the device may lose serial bus
communications once V_DD is powered up, and will return
to normal operation ONLY once V_DD and V_BAT are both
powered down together.
Layout Considerations
The ISL12022MR5421 contains a quarts crystal and
requires special handling during PC board assembly.
Excessive shock and vibrations should be avoided,
especially with automated handling equipment.
Ultrasound cleaning is not advisable as it subjects the
crystal to resonance and possible failure. See also Note 5
on page 5 in the specifications tables, which pertains to
solder reflow effects on oscillator accuracy.
The part of the package that has NC pins from pin 1 to 5
and from pin 16 to 20 contains the crystal. Low
frequency RTC crystals are known to pick up noise very
easily if layout precautions are not followed, even
embedded within a plastic package. Most instances of
erratic clocking or large accuracy errors can be traced to
the susceptibility of the oscillator circuit to interference
from adjacent high speed clock or data lines. Careful
26
FN7576.1
June 4, 2010