ISL12022MR5421 Datasheet, PDF (12/29 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated 5ppm

ISL12022MR5421
these registers will be retained. These registers will hold
the original power-down value until they are cleared by
setting CLRTS = 1 to clear the registers.
The normal power switching of the ISL12022MR5421 is
designed to switch into battery backup mode only if the
V_DD power is lost. This will ensure that the device can
accept a wide range of backup voltages from many types
of sources while reliably switching into backup mode.
Note that the ISL12022MR5421 is not guaranteed to
operate with V_BAT < 1.8V. If the battery voltage is
expected to drop lower than this minimum, correct
operation of the device, (especially after a V_DD
power-down cycle) is not guaranteed.
The minimum V_BAT to insure SRAM is stable is 1.0V.
Below that, the SRAM may be corrupted when V_DD
power resumes.
Real Time Clock Operation
The Real Time Clock (RTC) uses an integrated 32.768kHz
quartz crystal to maintain an accurate internal
representation of second, minute, hour, day of week,
date, month, and year. The RTC also has leap-year
correction. The clock also corrects for months having
fewer than 31 days and has a bit that controls 24-hour or
AM/PM format. When the ISL12022MR5421 powers up
after the loss of both V_DD and V_BAT, the clock will not
begin incrementing until at least one byte is written to
the clock register.
Single Event and Interrupt
The alarm mode is enabled via the MSB bit. Choosing
single event or interrupt alarm mode is selected via the
IM bit. Note that when the frequency output function is
enabled, the alarm function is disabled.
The standard alarm allows for alarms of time, date,
day of the week, month, and year. When a time alarm
occurs in single event mode, the IRQ/F_OUT pin will be
pulled low and the alarm status bit (ALM) will be set
to “1”.
The pulsed interrupt mode allows for repetitive or
recurring alarm functionality. Hence, once the alarm is
set, the device will continue to alarm for each occurring
match of the alarm and present time. Thus, it will alarm
as often as every minute (if only the nth second is set) or
as infrequently as once a year (if at least the nth month
is set). During pulsed interrupt mode, the IRQ/F_OUT pin
will be pulled low for 250ms and the alarm status bit
(ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit).
The alarm function can be enabled/disabled during
battery backup mode using the FOBATB bit. For more
information on the alarm, please see “ALARM Registers
(10h to 15h)” on page 20.
Frequency Output Mode
The ISL12022MR5421 has the option to provide a clock
output signal using the IRQ/F_OUT open drain output pin.
The frequency output mode is set by using the FO bits to
select 15 possible output frequency values from 1/32Hz
to 32kHz. The frequency output can be enabled/disabled
during Battery Backup mode using the FOBATB bit.
General Purpose User SRAM
The ISL12022MR5421 provides 128 bytes of user SRAM.
The SRAM will continue to operate in battery backup
mode. However, it should be noted that the I²C bus is
disabled in battery backup mode.
I²C Serial Interface
The ISL12022MR5421 has an I²C serial bus interface
that provides access to the control and status registers
and the user SRAM. The I²C serial interface is compatible
with other industry I²C serial bus protocols using a
bi-directional data signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL12022MR5421 provides both initial timing
correction and temperature correction due to variation
of the crystal oscillator. Analog and digital trimming
control is provided for initial adjustment, and a
temperature compensation function is provided to
automatically correct for temperature drift of the
crystal. Initial values for the initial AT and DT settings
(ITR0), temperature coefficient (ALPHA), crystal
capacitance (BETA), as well as the crystal turn-over
temperature (XTO), are preset internally and recalled to
RAM registers on power-up. These values can be
overwritten by the user although this is not
suggested as the resulting temperature
compensation performance will be compromised.
The compensation function can be enabled/disabled at
any time and can be used in battery mode as well.
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to
addresses [00h:2Fh]. The defined addresses and default
values are described in the Table 1. The battery backed
general purpose SRAM has a different slave address
(1010111x), so it is not possible to read/write that
section of memory while accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by
performing a byte or a page write operation directly to
any register address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (9 bytes): Address 07h to 0Fh.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address
16h to 1Ah.
12
FN7576.1
June 4, 2010