ISL6313B Datasheet, PDF (24/33 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6313B
pin voltage exceeds the V_OCP voltage of 2.0V, the
overcurrent protection circuitry activates. Since the IOUT pin
voltage is proportional to the output current, the overcurrent
trip level, I_OCP, can be set by selecting the proper value for
R_IOUT, as shown in Equation 24.
I_OCP = -_D----_C-----^6R-----^â‹-_â‹--^R-_R---^S--_I-_O-^E----_UT----_T-^â‹---^N-_â‹---₄---₀---₀--
(EQ. 24)
Once the output current exceeds the overcurrent trip level,
V_IOUT will exceed V_OCP and a comparator will trigger the
converter to begin overcurrent protection procedures.
At the beginning of an overcurrent shutdown, the controller
turns off both upper and lower MOSFETs and lowers
PGOOD. The controller will then immediately attempt to
soft-start. If the overcurrent fault remains, the trip-retry
cycles will continue until either the controller is disabled or
the fault is cleared. If five overcurrent events occur without
successfully completing soft-start, the controller will latch off
after the fifth try and must be reset by toggling EN before a
soft-start can be reinitiated. Note that the energy delivered
during trip-retry cycling is much less than during full-load
operation, so there is no thermal hazard.
OUTPUT CURRENT, 50A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
FIGURE 17. OVERCURRENT BEHAVIOR IN HICCUP MODE
Individual Channel Overcurrent Limiting
The ISL6313B has the ability to limit the current in each
individual channel without shutting down the entire regulator.
This is accomplished by continuously comparing the sensed
currents of each channel with a constant 140µA OCL
reference current as shown in Figure 16. If a channel’s
individual sensed current exceeds this OCL limit, the UGATE
signal of that channel is immediately forced low, and the
LGATE signal is forced high. This turns off the upper
MOSFET(s), turns on the lower MOSFET(s), and stops the
rise of current in that channel, forcing the current in the
channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel current falls
back below the 140µA reference.
During VID-on-the-fly transitions the OCL trip level is
boosted to prevent false overcurrent limiting events that can
occur. Starting from the beginning of a dynamic VID
transition, the overcurrent trip level is boosted to 196µA. The
OCL level will stay at this boosted level until 50µs after the
end of the dynamic VID transition, at which point it will return
to the typical 140µA trip level.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat-
dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(r_DS(ON)). In Equation 25, I_M is the maximum continuous
output current, I_PP is the peak-to-peak inductor current (see
Equation 1 on page 10), and d is the duty cycle (V_OUT/V_IN).
P_LOW(1)
=
r_DS(ON) ⋅
⎛
⎜
I--_{M---⎟⎞}
⎝ N⎠
2
⋅
(1
–
d)
+
I--_{L----(--P----P----)}²_---⋅_---(_--1-----–_-----d----)
12
(EQ. 25)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the
24
FN6809.0
November 6, 2008