ISL6313B Datasheet, PDF (22/33 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6313B
voltage to the final DAC voltage is referred to as tDB, and
can be calculated as shown in Equation 22:
tDB
=
V_V
I
D
⋅
R
S
S
⋅
8
⋅
10^–3
(
μ
s
)
(EQ. 22)
At the end of soft-start, PGOOD will immediately go high if
the VSEN voltage is within the undervoltage and overvoltage
limits.
V_OUT, 500mV/DIV
exceeding the DAC setting, the output drives are enabled at
the end of the soft-start period, leading to an abrupt correction
in the output voltage down to the DAC-set level.
Fault Monitoring and Protection
The ISL6313B actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 16
outlines the interaction between the fault monitors and the
power-good signal.
t_dA
t_dB
EN
PGOOD
500µs/DIV
FIGURE 14. SOFT-START WAVEFORMS
Pre-Biased Soft-Start
The ISL6313B also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
EN (5V/DIV)
T1 T2
T3
FIGURE 15. SOFT-START WAVEFORMS FOR ISL6313B-
BASED MULTI-PHASE CONVERTER
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by
the DAC setting. Should the output be pre-charged to a level
I_AVG
100µA
+
OCP
-
VDAC + RGND
+175mV
OR
SS
+225mV
+
OCL
-
I₁
140µA
REPEAT FOR
EACH CHANNEL
+
OCP
-
IOUT
V_OCP
1.260V
SOFT-START, FAULT
AND CONTROL LOGIC
VSEN
-
OVP
+
PGOOD
-350mV
VDAC + RGND
-
UV
+
ISL6313B INTERNAL CIRCUITRY
FIGURE 16. POWER GOOD AND PROTECTION CIRCUITRY
Power-Good Signal
The power-good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6313B is regulating the
output voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied through a resistor to
a voltage source that’s equal to or less then VCC.
For Intel mode of operation, PGOOD indicates whether VSEN
is within specified overvoltage and undervoltage limits after a
fixed delay from the end of soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
EN, POR, or one of the no-CPU VID codes. In the event of
an overvoltage or overcurrent condition, or a no-CPU VID
code, the controller latches off and PGOOD will not return
high until EN is toggled and a successful soft-start is
22
FN6809.0
November 6, 2008