ISL6740 Datasheet, PDF (23/29 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, 1SL6741
A block diagram of the feedback control loop follows in
Figure 19.
PWM
POWER
STAGE
V_OUT
ISOLATION
ERROR AMPLIFIER
Z₂
-
Z₁
+ REF
FIGURE 19. CONTROL LOOP BLOCK DIAGRAM
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. A Type 3 error
amplifier configuration was selected.
40
30
20
10
0
-10
-20
10
100
1•10³
1•10⁴
1•10⁵
FREQUENCY (Hz)
FIGURE 21A. CONTROL-TO-OUTPUT GAIN
1•10⁶
50
0
V_OUT
-50
V_ERR
-
+ REF
FIGURE 20. TYPE 3 ERROR AMPLIFIER
The control to output transfer function may be represented
as [1]
v_----o-
v_c
=
----^V----^I--^N------
V_S • 2
•
N_-----S--
N_P
•
-----------------¹-----+-----^{ω----s-----z}-------------------
1
+
--------^s--------
(Q)ω_o
+
⎛
⎝
ω^---s--_o^{-⎠⎞}
2
(EQ. 26)
where
Q = _ω-----_o^R----_•-^o----_L-
ω_o
=
-----¹------
LC
or
ω_z
=
-----¹------
R_cC
or
f_o
=
---------¹----------
2π LC
f_z = ₂----_π----_R-¹----_c---_C--
R_o = Output Load Resistance
L = Output Inductance
C = Output Capacitance
R_c = Output Capacitance ESR
V_S = Sawtooth Ramp Amplitude
Gain and phase plots of (Equation 26) appear below using
L = 4.0μH, C = 150μF, Rc = 28mΩ, Ro = 1.2Ω, and VIN = 75V.
23
-100
-150
-200
10
100
1•10³
1•10⁴
1•10⁵
FREQUENCY (Hz)
FIGURE 21B. CONTROL-TO-OUTPUT PHASE
1•10⁶
The Type 3 compensation configuration has three poles and
two zeros. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the Typical Application Schematic for
the regulated output, the remaining poles and zeros for the
compensator are located at:
f_p2 = ₂----_π-----_•----_R-----₂--¹-₁-----_•-----_C----₂----₀-
(EQ. 27)
f_p3
≈
------------------¹-------------------
2π • R4 • C22
C19 » C20
(EQ. 28)
f_z1 = ₂----_π-----_•----_R-----₂--¹--₁----_•-----_C----₁----₉-
(EQ. 29)
f_z2 ≈ ₂----_π-----_•----_R-----₂--¹-₃-----_•-----_C----₂----₂-
R23 » R4
(EQ. 30)
From (Equation 26), it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitor and
inductor, and the output capacitance ESR. These variations
must be considered when compensating the control loop.
The worst case small signal operating point for a voltage
mode converter tends to be at maximum Vin, maximum load,
maximum C_OUT, and minimum ESR.
FN9111.4
July 13, 2007