ISL6740 Datasheet, PDF (20/29 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, 1SL6741
method to achieve this. The divider between RTC and GND
formed by R13 and R15 determines the percent of maximum
duty cycle that corresponds to a short circuit. The divider
ratio formed by R13 and R15 is
---------^R-----¹----⁵----------
R13 + R15
=
-----------¹----^.-²----⁷---^k-------------
1.27k + 17.4k
=
0.068
(EQ. 24)
Therefore, the duty cycle that corresponds to a short circuit
is 6.8% of D max (97.9%), or ~6.6%.
Performance
The major performance criteria for the converter are
efficiency, and to a lesser extent, load regulation. Efficiency,
load regulation and line regulation performance are
demonstrated in the following Figures.
100
95
90
85
80
75
70
0 123456789
LOAD CURRENT (A)
FIGURE 10. EFFICIENCY vs LOAD V_IN = 48V_t
regulation is not required, such as those application that use
downstream DC/DC converters, this design approach is
viable.
Waveforms
Typical waveforms can be found in the following Figures.
Figure 13 shows the output voltage during start up.
FIGURE 13. OUTPUT SOFT-START
Figure 14 shows the output voltage ripple and noise at a 5A
load.
12.5
12.25
12.00
11.75
11.50
11.25
11
0
1
2
3
4
5
6
7
8
9
LOAD CURRENT (A)
FIGURE 11. LOAD REGULATION AT V_IN = 48V
14.0
13.5
13.0
12.5
12.0
11.5
11.0
45 46 47 48 49 50 51 52 53 54
INPUT VOLTAGE (V)
FIGURE 12. LINE REGULATION AT I_OUT = 1A
As expected, the output voltage varies considerably with line
and load when compared to an equivalent converter with
closed loop feedback. However, for applications where tight
20
FIGURE 14. OUTPUT RIPPLE AND NOISE (20MHz BW)
Figures 15 and 16 show the voltage waveforms at the
switching node shared by the upper FET source and the lower
FET drain. In particular, Figure 16 shows near ZVS operation
at 8A of load when the upper FET is turning off and the lower
FET turning on. There is insufficient energy stored in the
leakage inductance to allow complete ZVS operation.
However, since the energy stored in the node capacitance is
proportional to V², a significant portion of the energy is still
recovered. Figure 17 shows the switching transition between
outputs, OUTA and OUTB during steady state operation. The
deadtime duration of 48.6ns is clearly shown.
FN9111.4
July 13, 2007