ISL6740 Datasheet, PDF (13/29 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, 1SL6741
The voltage hysteresis created by the switched current
source and the external impedance is generally small due to
the large resistor divider ratio required to scale the input
voltage down to the UV threshold level. A small capacitor
placed between the UV input and ground may be required to
filter noise out.
V_IN
R1
R3
R2
1.00V +
-
10μA
ON
FIGURE 5. UV HYSTERESIS
As V_IN decreases to a UV condition, the threshold level is:
V_IN(DOWN)
=
R_-----1_-----+-----R_-----2_--
R2
V
(EQ. 7)
The hysteresis voltage, ΔV, is:
ΔV
=
10^–5 •
〈
R1
+
R3
•
⎛
⎝
R_-----1_{---R--+---2--}R_-----2_{--⎠⎞}
〉
V
(EQ. 8)
Setting R3 equal to zero results in the minimum hysteresis,
and yields:
ΔV = 10^–5 • R1
V
(EQ. 9)
As V_IN increases from a UV condition, the threshold level is:
V_IN(UP) = V_IN(DOWN) + ΔV
V
(EQ. 10)
Over Current Operation
ISL6740 - Overcurrent delayed shutdown is enabled once
the soft-start cycle is complete. If an overcurrent condition is
detected, the soft-start charging current source is disabled
and the soft-start capacitor is allowed to discharge through a
15μA source. At the same time a 50μs re-triggerable one-
shot timer is activated. It remains active for 50μs after the
overcurrent condition ceases. If the soft-start capacitor
discharges by more then 0.25V to 4.25V, the output is
disabled and the Fault signal asserted. This state continues
until the soft-start voltage reaches 270mV, at which time a
new soft-start cycle is initiated. If the overcurrent condition
stops at least 50μs prior to the soft-start voltage reaching
4.25V, the soft-start charging currents revert to normal
operation and the soft-start voltage is allowed to recover.
The duration of the OC shutdown period can be increased
by adding a resistor between VREF and SS. The value of
the resistor must be large enough so that the minimum
specified SS discharge current is not exceeded. Using a
422kΩ resistor, for example, will result in a small current
being injected into SS, effectively reducing the discharge
current. This will increase the OFF time by about 60%,
nominally. The external pull-up resistor will also decrease
the SS duration, so its effect should be considered when
selecting the value of the SS capacitor.
Latching OC shutdown is also possible by using a lower
valued resistor between VREF and SS. If the SS node is not
allowed to discharge below the SS reset threshold, the IC
will not recover from an overcurrent fault. The value of the
resistor must be low enough so that the maximum specified
discharge current is not sufficient to pull SS below 0.33V. A
200kΩ resistor, for example, prevents SS from discharging
below ~0.4V. Again, the external pull-up resistor will
decrease the SS duration, so its effect should be considered
when selecting the value of the SS capacitor.
ISL6741 - Overcurrent results in pulse-by-pulse duty cycle
reduction as occurs in any peak current mode controller. This
results in a well controlled decrease in output voltage with
increasing current beyond the overcurrent threshold. An
overcurrent condition in the ISL6741 will not cause a
shutdown.
Short Circuit Operation
A short circuit condition is defined as the simultaneous
occurrence of current limit and a reduced duty cycle. The
degree of reduced duty cycle is user adjustable using the
SCSET input. A resistor divider between either R_TD or R_TC
and GND to RCSET sets a threshold that is compared to the
voltage on the timing capacitor, C_T. The resistor divider
percentage corresponds to the fraction of the maximum duty
cycle below which a short circuit may exist. If the timing
capacitor voltage fails to exceed the threshold before an
overcurrent pulse is detected, a short circuit condition exists.
A shutdown and soft-start cycle will begin if 8 short circuit
events occur within 32 oscillator cycles. Connecting SCSET
to GND disables this feature.
Since the current sourced from both R_TC and R_TD determine
the charge and discharge currents for the timing capacitor,
the effect of the SCSET divider must be included in the
timing calculations. Typically the resistor between R_TC and
GND is formed by two series resistors with the center node
connected to SCSET.
Alternatively, SCSET may be set using a voltage between
0V and 2V. This voltage divided by 2 determines the
percentage of the maximum duty cycle that corresponds to a
short circuit when current limit is active. For example, if the
maximum duty cycle is 95% and 1V is applied to SCSET,
then the short circuit duty cycle is 50% of 95% or 47.5%.
13
FN9111.4
July 13, 2007