ISL6564A Datasheet, PDF (23/28 Pages) Intersil Corporation – Multiphase PWM Controller with Linear 6-Bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

C₂ (OPTIONAL)
R_C ^CC
COMP
R_FB
+
V_DROOP
-
FB
IDROOP
VDIFF
ISL6564A
C₁
R₁
C₂
R_C ^CC
COMP
FB
R_FB
IDROOP
VDIFF
FIGURE 18. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6564A CIRCUIT
The feedback resistor, R_FB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f₀. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
Case 1:
---------1----------
2π LC
>
f₀
R_C
=
R_FB
2----π_{----f--0---V-----p---p-------L----C---}
0.75 V _{I N}
C_C = _2----π----0V---.-_P-7---5_P----VR----^I-_F-^N--_B----f--₀--
Case 2:
---------1----------
2π LC
≤
f₀
<
--------------1---------------
2πC(ESR)
R_C
=
R_FB
V-----_P----P----(_--2----π_----)_--²_----f--0--²_{----L----C---}
0.75 V_IN
C_C
=
--------------------0----.-7----5---V-----^I--^N---------------------
(2π)² f₀₂ V_PPR_FB LC
(EQ. 24)
Case 3:
f₀
>
--------------1---------------
2πC(ESR)
R_C
=
R_FB
--------2----^π----f--⁰---V-----^p---^p---L---------
0.75 V_IN (ESR)
C_C
=
-0---.--7---5----V----^I--^N----⁽--E-----S----R-----⁾-------C---
2πV_PPR_FBf₀ L
In Equation 24, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
23
FIGURE 19. COMPENSATION CIRCUIT FOR ISL6564A BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
the bulk output-filter capacitance; and V_PP is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 18). Keep
a position available for C₂, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 24
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 24 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 19, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f_HF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f_HF = 10f₀, but it can be
higher if desired. Choosing f_HF to be lower than 10f₀ can
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 24, R_FB is selected arbitrarily. The remaining
FN6285.1
March 20, 2007