ISL6564A Datasheet, PDF (14/28 Pages) Intersil Corporation – Multiphase PWM Controller with Linear 6-Bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

ISL6564A
IL
L
R_SENSE V_OUT
C_OUT
ISL6564A INTERNAL CIRCUIT
R_ISEN(n)
I_n
SAMPLE
&
HOLD
ISEN-(n)
+
-
ISEN+(n)
ISEN
=
IL
-R----S-----E----N-----S----E---
RISEN
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
MOSFET r_DS(ON) SENSING
The controller can also sense the channel load current by
sampling the voltage across the lower MOSFET r_DS(ON)
(see Figure 6). The amplifier is ground-reference by
connecting the ISEN- input to the source of the lower
MOSFET. ISEN+ connects to the PHASE node through a
resistor R_ISEN. The voltage across R_ISEN is equivalent to
the voltage drop across the r_DS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN+
pin is proportional to the channel current I_L. The ISEN
current is then sampled and held after sufficient settling time.
The sampled current I_n, is used for channel-current balance,
load-line regulation, and overcurrent protection. From
Figure 6, Equation 7 for I_SEN is derived.
ISEN
=
IL
-r--D-----S----⁽---O-----N-----⁾
RISEN
I_n
SAMPLE
&
HOLD
-
+
ISEN+(n)
R_ISEN
(PTC)
ISEN-(n)
V_IN
I_L
-
IL rDS_(ON)
+
N-CHANNEL
MOSFETs
ISL6564A INTERNAL CIRCUIT EXTERNAL CIRCUIT
FIGURE 6. MOSFET r_DS(ON) CURRENT-SENSING CIRCUIT
I_SEN
=
I_L
r---_{D----S----(--O----N-----)}
R_ISEN
(EQ. 7)
where I_L is the channel current. Since MOSFET r_DS(ON)
increases with temperature, a PTC resistor should be
chosen for R_ISEN to compensate for this change.
Channel-Current Balance
The sampled currents I_n, from each active channel are
summed together and divided by the number of active
channels. The resulting cycle average current I_AVG, provides
a measure of the total load current demand on the converter
during each switching cycle. Channel current balance is
achieved by comparing the sampled current of each channel
to the cycle average current, and making an appropriate
adjustment to each channel pulse width based on the error.
Intersil’s patented current-balance method is illustrated in
Figure 7, with error correction for channel 1 represented. In
the figure, the cycle average current combines with the
channel 1 sample, I₁, to create an error signal I_ER. The
filtered error signal modifies the pulse width commanded by
V_COMP to correct any unbalance and force I_ER toward zero.
The same method for error signal correction is applied to
each active channel.
+
V_COMP
-
FILTER f(jω)
+
-
SAWTOOTH SIGNAL
I_ER
I_AVG
÷N
Σ
-
+
PWM1
I₄ *
I₃ *
I₂
I₁
NOTE: *Channels 3 and 4 are optional.
FIGURE 7. CHANNEL 1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Channel current balance is essential in realizing the thermal
advantage of multiphase operation. The heat generated in
down converting is dissipated over multiple devices and a
greater area. The designer avoids the complexity of driving
multiple parallel MOSFETs, and the expense of using heat
sinks and nonstandard magnetic materials.
Voltage Regulation
The integrating compensation network shown in Figure 8
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6564A to include the
combined tolerances of each of these elements.
The output of the error amplifier, V_COMP, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry which control
voltage regulation is illustrated in Figure 8.
14
FN6285.1
March 20, 2007