ISL6564A Datasheet, PDF (17/28 Pages) Intersil Corporation – Multiphase PWM Controller with Linear 6-Bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

ISL6564A
FB
DYNAMIC
VID D/A
DAC
R_REF
E/A
REF
VCC
OR
GND
-
2.0V
+
+
0.5V
-
R_OFS
OFS
ISL6564A
VCC
GND
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6564A
Assuming the microprocessor controls the VID change at 1
bit every T_VID, the relationship between the time constant of
R_REF and C_REF network and T_VID is given by Equation 12.
C_REF R_REF = k T_VID
(EQ. 12)
Where, T_VID = 4μs, k is the number of the internal VID
change cycle. If Typically R_REF is selected to be 1kΩ, the
allowable delay time for VR to respond to new VID code is 5
VID change cycles (totally 20μs), the value of C_REF should
be 22nF based on Equation 12.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, PGOOD asserts
logic 1.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6564A
is released from shutdown mode.
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6564A checks the VID inputs at the three edges of
16MHz clock. If the VID code is found to have changed, the
controller waits half of a complete cycle before executing a
12.5mV change. If during the half-cycle wait period, the
difference between DAC level and the new VID code
changes sign, no change is made. If the VID code is more
than 1 bit higher or lower than the DAC (not recommended),
the controller will execute step-up and step down VID
change at a speed of 12.5mV every 4μs until VID and DAC
are equal.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R_REF and C_REF is required for an ISL6564A
based voltage regulator. The selection of R_REF is based on
the desired offset as detailed above in Output-Voltage Offset
Programming. The selection of C_REF is based on the time
duration for 1 bit VID change and the allowable delay time.
ISL6564A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
POR
CIRCUIT
VCC
+12V
ENABLE
COMPARATOR
+
-
10.7kΩ
EN
1.40kΩ
1.23V
SOFT-START
AND
FAULT LOGIC
ENLL
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6564A is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6564A will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications).
17
FN6285.1
March 20, 2007