ISL6564A Datasheet, PDF (16/28 Pages) Intersil Corporation – Multiphase PWM Controller with Linear 6-Bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

ISL6564A
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
VID5 VID4 VID3 VID2 VID1 VID0
VDAC
400 200 100 50
25
12.5
mV mV mV mv
mV
mV
0
1
1
0
1
1
0.8625V
0
1
1
0
1
0
0.8500V
0
1
1
0
0
1
0.8375V
0
1
1
0
0
0
0.8250V
0
1
0
1
1
1
0.8125V
0
1
0
1
1
0
0.8000V
0
1
0
1
0
1
0.7875V
0
1
0
1
0
0
0.7750V
0
1
0
0
1
1
0.7625V
0
1
0
0
1
0
0.7500V
0
1
0
0
0
1
0.7375V
0
1
0
0
0
0
0.7250V
0
0
1
1
1
1
0.7125V
0
0
1
1
1
0
0.7000V
0
0
1
1
0
1
0.6875V
0
0
1
1
0
0
0.6750V
0
0
1
0
1
1
0.6625V
0
0
1
0
1
0
0.6500V
0
0
1
0
0
1
0.6375V
0
0
1
0
0
0
0.6250V
0
0
0
1
1
1
0.6125V
0
0
0
1
1
0
0.6000V
0
0
0
1
0
1
0.5875V
0
0
0
1
0
0
0.5750V
0
0
0
0
1
1
0.5625V
0
0
0
0
1
0
0.5500V
0
0
0
0
0
1
0.5375V
0
0
0
0
0
0
0.525V
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, I_AVG, flows from FB through a
load-line regulation resistor, R_FB. The resulting voltage drop
across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
V_DROOP = I_AVG R_FB
(EQ. 8)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
V_OUT
=
V_REF
–
V_O
F
F
SET
–
⎛
⎜
⎝
I--_{O-----U----T--}
4
------R----^X-------
R_ISEN
⎞
R _{F B⎠⎟}
(EQ. 9)
Where V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_OUT is the total output current
of the converter, R_ISEN is the sense resistor in the ISEN line,
and R_FB is the feedback resistor. R_X has a value of DCR,
r_DS(ON), or R_SENSE depending on the sensing method.
Output-Voltage Offset Programming
The ISL6564A allows the designer to accurately adjust the
offset voltage. When a resistor, R_OFS, is connected between
OFS to VCC, the voltage across it is regulated to 2.0V. This
causes a proportional current (I_OFS) to flow into OFS. If
R_OFS is connected to ground, the voltage across it is
regulated to 0.5V, and I_OFS flows out of OFS. A resistor
between DAC and REF, R_REF, is selected so that the
product (I_OFS x R_OFS) is equal to the desired offset voltage.
These functions are shown in Figure 9.
As it may be noticed in Figure 9, the OFSOUT pin must be
connected to the REF pin for this current injection to function
in ISL6564A. The current flow through R_REF creates an
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to VCC):
R_OFS
=
-²-----^×-----^R----^R-----^E----^F--
V_OFFSET
(EQ. 10)
For Negative Offset (connect R_OFS to GND):
R_OFS
=
0_----._--5_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 11)
16
FN6285.1
March 20, 2007