ISL6310 Datasheet, PDF (23/27 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6310
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20
log
⎛
⎝
RR-----21--_⎠⎞
0
20log ^d-----^M-----^A----^X------^â‹----V----I--N---
V_OSC
G_FB
G_CL
LOG
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 23. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the per-channel switching frequency, F_SW.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔV_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
ΔV
≈
(ESL)
⋅
-d---i
dt
+
(ESR)
⋅
ΔI
(EQ. 39)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 9 and Equation 2), a voltage develops across the bulk
capacitor ESR equal to I_C,PP (ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
voltage, V_PP(MAX), determines the lower limit on the
inductance.
L
≥
(ESR)
⎛
⎝
V_IN
–
N
⋅
V _{O U T⎠⎞}
⋅
V_OUT
-------------------------------------------------------------------
F_SW ⋅ V_IN ⋅ V_PP(MAX)
(EQ. 40)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV_MAX. This places an upper limit on inductance.
Equation 41 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 42
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
2 ⋅ N ⋅ C ⋅ V_O
L
≤
---------------------------------
(ΔI)²
⋅
ΔV_MAX – (ΔI ⋅ ESR)
(EQ. 41)
L
≤
-⁽--1---.--2---5----⁾----^â‹---N-----^â‹---C---
(ΔI)²
⋅
ΔV_MAX – (ΔI ⋅ ESR)
⋅
⎛
⎝
V_IN
–
V_{O⎠⎞}
(EQ. 42)
23
FN9209.4
August 7, 2008