ISL6310 Datasheet, PDF (22/27 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6310
and C₃) in Figures 20 and 21. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R₁ (1kΩ to 5kΩ, typically). Calculate
value for R₂ for desired converter bandwidth (F₀). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R₂ value needs be
multiplied by a factor of (R_P1 + R_S1)/R_P1. The remainder
of the calculations remain unchanged, as long as the
compensated R₂ value is used.
R₂ = -_d--^V-_M----^O-_A---^S-_X---^C--_â‹---_V^â‹---^R-_I--_N--¹---_â‹-^â‹--_F-^F---_L-⁰--_C---
(EQ. 30)
C₂
COMP
R₂
C₁
-
FB
E/A ⁺
VREF
R₃
C₃
R₁
VDIFF
-
RGND
+
VSEN
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_OUT
V_IN
UGATE
PHASE
LGATE
L
DCR
C
ESR
ISL6310 EXTERNAL CIRCUIT
FIGURE 22. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
2. Calculate C₁ such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost at F_LC).
C₁
=
-----------------------¹-----------------------
2π ⋅ R₂ ⋅ 0.5 ⋅ F_LC
(EQ. 31)
3. Calculate C₂ such that F_P1 is placed at F_CE.
C₂ = -₂---_π-----_â‹---_R-----₂----_â‹---_C-^C----₁-¹---_â‹---_F----_C----_E-----–-----₁-
(EQ. 32)
4. Calculate R₃ such that F_Z2 is placed at F_LC. Calculate C₃
such that F_P2 is placed below F_SW (typically, 0.5 to 1.0
times F_SW). F_SW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F_P2 lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
R₃
=
--------^R-----¹--------
F_{----S----W----}
F_LC
–
1
C₃ = ₂----_π-----_â‹---_R-----₃----_â‹--¹-₀---_.--₇-----_â‹---_F----_S----_W---
(EQ. 33)
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
⋅
-------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---^E-----^S----^R------^â‹---^C----------------------------------
1 + s(f) ⋅ (ESR + DCR) ⋅ C + s²(f) ⋅ L ⋅ C
G_FB(f) = -_s---₍-¹-_f--₎--+--_â‹---^sR---⁽--₁-^f--⁾-_â‹--^â‹-₍--^RC-----²¹----^â‹_+---^C--_C---¹--₂----₎ ⋅
(EQ. 34)
------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---⁽---^R----¹-----+-----^R----³----⁾---^â‹---^C-----³-------------------------------
(
1
+
s
(
f)
⋅
R₃
⋅
C₃
)
⋅
⎛
⎜
⎝
1
+
s
(
f
)
⋅
R₂
⋅
⎛
⎜
⎝
C^-C----₁^{-1----+⋅---C-}C^----2-₂^-_{⎠⎟⎞⎠⎟⎞}
G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where, s(f) = 2π ⋅ f ⋅ j
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
--------------¹----------------
2π ⋅ R₂ ⋅ C₁
(EQ. 35)
F_Z2
=
------------------------¹-------------------------
2π ⋅ (R₁ + R₃) ⋅ C₃
(EQ. 36)
F_P1
=
---------------------¹-----------------------
2
π
⋅
R₂
⋅
-^C-----¹----^â‹---^C-----²--
C₁ + C₂
F_P2
=
--------------¹----------------
2π ⋅ R₃ ⋅ C₃
(EQ. 37)
(EQ. 38)
Figure 23 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 against the capabilities of the error
amplifier. The closed loop gain, G_CL, is constructed on the
log-log graph of Figure 23 by adding the modulator gain,
G_MOD (in dB), to the feedback compensation gain, G_FB (in
22
FN9209.4
August 7, 2008