ISL6310 Datasheet, PDF (10/27 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6310
C_IN CURRENT
Q1 D-S CURRENT
Q2 D-S CURRENT
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR 2-PHASE
CONVERTER
Figures 25 and 26 in the section entitled “Input Capacitor
Selection” on page 24 can be used to determine the input
capacitor RMS current based on load current, duty cycle,
and the number of channels. They are provided as aids in
determining the optimal input capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6310
is two. One switching cycle is defined as the time between
the internal PWM1 pulse termination signals. The pulse
termination signal is the internally generated clock signal
that triggers the falling edge of PWM1. The cycle time of the
pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
PWM1 to go low. The PWM1 transition signals the internal
channel 1 MOSFET driver to turn off the Channel 1 upper
MOSFET and turn on the Channel 1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
terminates 1/2 of a cycle after the PWM1 pulse.
One switching cycle for the ISL6310 is defined as the time
between consecutive PWM pulse terminations (turn-off of
the upper MOSFET on a channel). Each cycle begins when
a switching clock signal commands the upper MOSFET to
go off. The other channel’s upper MOSFET conduction is
terminated 1/2 of a cycle later.
Once a PWM pulse transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
V_COMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 3. When the modified
V_COMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The internal MOSFET driver detects the
change in state of the PWM signal and turns off the
synchronous MOSFET and turns on the upper MOSFET.
The PWM signal will remain high until the pulse termination
signal marks the beginning of the next cycle by triggering the
PWM signal low.
Single phase operation can be selected by connecting 2PH
to GND.
Channel Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I_n,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I_AVG, provides a measure of the total load
current demand on the converter during each switching
cycle. Channel current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current
balance method is illustrated in Figure 3, with error
correction for Channel 1 represented. In Figure 3, the cycle
average current, I_AVG, is compared with the Channel 1
sample, I₁, to create an error signal I_ER.
The filtered error signal modifies the pulse width
commanded by V_COMP to correct any unbalance and force
I_ER toward zero. The same method for error signal
correction is applied to each active channel.
+
V_COMP
-
FILTER f(s)
PWM1
+
-
SAWTOOTH SIGNAL
TO GATE
CONTROL
LOGIC
I_ER
I_AVG
-
÷N
+
I₂
Σ
I₁
NOTE: CHANNEL 2 IS OPTIONAL.
FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Current Sampling
In order to realize proper current balance, the currents in
each channel must be sampled every switching cycle. This
sampling occurs during the forced off-time, following a PWM
10
FN9209.4
August 7, 2008