ISL6741_14 Datasheet, PDF (22/28 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, ISL6741
Other duty ranges are possible, but are still limited to a 2:1 ratio.
The voltage applied to V_ERROR must be scaled to the peak-to-
peak voltage on C_T, and offset by the valley voltage. Since the
peak-to-peak C_T voltage is 2.00V nominal, the voltage at the
output of U100A must be divided by 2.0V to obtain the desired
duty cycle. For example, if an 80% duty cycle was required at the
minimum operating voltage, the output of U100A must be 1.60V
(80% of 2.00V). From (Equation 25), the divider voltage must be
set to 1.4V for the input voltage that corresponds to the 80% duty
cycle.
It should be noted that the synchronous rectifiers (SRs), being
driven from the transformer secondary, are only gated on during
the ON time of the primary FETs. Conduction continues through
the body diodes during the OFF time when operating in
continuous inductor current mode. This mode of operation
usually results in significant conduction and switching losses in
the SR FETs. These losses may be reduced considerably by either
adding schottky diodes in parallel to the SR FETs or by driving the
SR FETs directly with a control signal.
Adding Regulation - Closed Loop Feedback
The second Typical Application schematic adds closed loop
feedback with isolation. The ISL6740EVAL2Z demonstration
platform implements this design and is available for evaluation.
The input voltage range was increased to 36V to 75V, which
necessitates a few modifications to the open loop design. The
output inductor value was increased to 4.0μH, schottky rectifier
CR4 was added to minimize SR FET body diode conduction, the
turns ratio of the main transformer was changed to 4:3, and the
synchronous rectifier gate drives were modified. The design
process is essentially the same as it was for the unregulated
version, so only the feedback control loop design will be
discussed.
The major components of the feedback control loop are a
programmable shunt regulator and an opto-coupler. The opto-
coupler is used to transfer the error signal across the isolation
barrier. The opto-coupler offers a convenient means to cross the
isolation barrier, but it adds complexity to the feedback control
loop. It adds a pole at about 10kHz and a significant amount of
gain variation due the current transfer ratio (CTR). The CTR of the
opto-coupler varies with initial tolerance, temperature, forward
current, and age.
A block diagram of the feedback control loop follows in
Figure 19.
PWM
ISOLATION
POWER
STAGE
ERROR AMPLIFIER
Z₂
-
Z₁
+ REF
V_OUT
FIGURE 19. CONTROL LOOP BLOCK DIAGRAM
The loop compensation is placed around the Error Amplifier (EA)
on the secondary side of the converter. A Type 3 error amplifier
configuration was selected.
V_OUT
V_ERR
-
+ REF
FIGURE 20. TYPE 3 ERROR AMPLIFIER
The control to output transfer function may be represented as [1]
v_---o--
v_c
=
V^----_S^V----I-•^N----2^--
•
-^N----^S-
N_P
•
-----------------¹-----+------^ω---^s-----z-----------------
1
+
-------^s--------
(Q)ω_o
+
⎛
⎝
-_ω--^s--_o-_⎠⎞
2
(EQ. 26)
where:
Q = -_ω----_o^R----_•^o----_L--
ω_o
=
----¹------
LC
or
f_o
=
--------¹----------
2π LC
ω_z
=
----¹-----
R_cC
or
f_z
=
--------¹---------
2πR_cC
R_o = Output Load Resistance
L = Output Inductance
C = Output Capacitance
R_c = Output Capacitance ESR
V_S = Sawtooth Ramp Amplitude
Gain and phase plots of (Equation 26) appear below using
L = 4.0μH, C = 150μF, Rc = 28mΩ, Ro = 1.2Ω, and VIN = 75V.
22
FN9111.6
December 2, 2011