ISL6741_14 Datasheet, PDF (13/28 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, ISL6741
The hysteresis voltage, ΔV, is:
ΔV
=
10^–5 •
〈
R
1
+
R3
•
⎛
⎝
R_-----1_{---R--+--2---}R_----2_{--⎠⎞}
〉
V
(EQ. 8)
Setting R3 equal to zero results in the minimum hysteresis, and
yields:
ΔV = 10^–5 • R1
V
(EQ. 9)
As V_IN increases from a UV condition, the threshold level is:
V_IN(UP) = V_IN(DOWN) + ΔV
V
(EQ. 10)
Overcurrent Operation
ISL6740 - Overcurrent delayed shutdown is enabled once the
soft-start cycle is complete. If an overcurrent condition is
detected, the soft-start charging current source is disabled and
the soft-start capacitor is allowed to discharge through a 15μA
source. At the same time a 50μs re-triggerable one-shot timer is
activated. It remains active for 50μs after the overcurrent
condition ceases. If the soft-start capacitor discharges by more
then 0.25V to 4.25V, the output is disabled and the Fault signal
asserted. This state continues until the soft-start voltage reaches
270mV, at which time a new soft-start cycle is initiated. If the
overcurrent condition stops at least 50μs prior to the soft-start
voltage reaching 4.25V, the soft-start charging currents revert to
normal operation and the soft-start voltage is allowed to recover.
The duration of the OC shutdown period can be increased by
adding a resistor between VREF and SS. The value of the resistor
must be large enough so that the minimum specified SS
discharge current is not exceeded. Using a 422kΩ resistor, for
example, will result in a small current being injected into SS,
effectively reducing the discharge current. This will increase the
OFF time by about 60%, nominally. The external pull-up resistor
will also decrease the SS duration, so its effect should be
considered when selecting the value of the SS capacitor.
Latching OC shutdown is also possible by using a lower valued
resistor between VREF and SS. If the SS node is not allowed to
discharge below the SS reset threshold, the IC will not recover
from an overcurrent fault. The value of the resistor must be low
enough so that the maximum specified discharge current is not
sufficient to pull SS below 0.33V. A 200kΩ resistor, for example,
prevents SS from discharging below ~0.4V. Again, the external
pull-up resistor will decrease the SS duration, so its effect should
be considered when selecting the value of the SS capacitor.
ISL6741 - Overcurrent results in pulse-by-pulse duty cycle
reduction as occurs in any peak current mode controller. This
results in a well controlled decrease in output voltage with
increasing current beyond the overcurrent threshold. An
overcurrent condition in the ISL6741 will not cause a shutdown.
Short Circuit Operation
A short circuit condition is defined as the simultaneous
occurrence of current limit and a reduced duty cycle. The degree
of reduced duty cycle is user adjustable using the SCSET input. A
resistor divider between either R_TD or R_TC and GND to RCSET
sets a threshold that is compared to the voltage on the timing
capacitor, C_T. The resistor divider percentage corresponds to the
fraction of the maximum duty cycle below which a short circuit
may exist. If the timing capacitor voltage fails to exceed the
threshold before an overcurrent pulse is detected, a short circuit
condition exists. A shutdown and soft-start cycle will begin if 8
short circuit events occur within 32 oscillator cycles. Connecting
SCSET to GND disables this feature.
Since the current sourced from both R_TC and R_TD determine the
charge and discharge currents for the timing capacitor, the effect
of the SCSET divider must be included in the timing calculations.
Typically the resistor between R_TC and GND is formed by two
series resistors with the center node connected to SCSET.
Alternatively, SCSET may be set using a voltage between 0V and
2V. This voltage divided by 2 determines the percentage of the
maximum duty cycle that corresponds to a short circuit when
current limit is active. For example, if the maximum duty cycle is
95% and 1V is applied to SCSET, then the short circuit duty cycle
is 50% of 95% or 47.5%.
Fault Conditions
A fault condition occurs if V_REF falls below 4.65V, the UV input
falls below 1.00V, the thermal protection is triggered, or if OTS
faults. When a fault is detected, OUTA and OUTB outputs are
disabled, the Fault signal is asserted, and the soft-start capacitor
is quickly discharged. When the fault condition clears and the
soft-start voltage is below the reset threshold, a soft-start cycle
begins. The Fault signal is high impedance during the soft-start
cycle.
An overcurrent condition that results in shutdown (ISL6740), or a
short circuit shutdown also cause assertion of the Fault signal.
The difference between a current fault and the faults described
earlier is that the soft-start capacitor is not quickly discharged.
The initiation of a new soft-start cycle is delayed while the soft-
start capacitor is discharged at a 15μA rate. This keeps the
average output current to a minimum.
Thermal Protection
Two methods of over-temperature protection are provided. The
first method is an on board temperature sensor that protects the
device should the junction temperature exceed 145°C. There is
approximately 15°C of hysteresis.
The second method uses an internal comparator with a 2.5V
reference (V_REF/2). The non-inverting input to the comparator is
accessible through the OTS pin. A thermistor or thermal sensor
located at or near the area of interest may be connected to this
input. There is a nominal 25μA switched current source used to
create hysteresis. The current source is active only during an OT
fault; otherwise, it is inactive and does not affect the node
voltage. The magnitude of the hysteresis is a function of the
external resistor divider impedance. Either a positive
temperature coefficient (PTC) or a negative temperature
13
FN9111.6
December 2, 2011