ISL6741_14 Datasheet, PDF (14/28 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, ISL6741
coefficient (NTC) thermistor may be used. If a NTC is desired,
position R1 may be substituted.
V_REF
R1
R2
V_REF
ON
25μA
+
R3
V_REF/2 ^-
FIGURE 6. OTS HYSTERESIS
If a PTC is desired, then position R2 may be substituted. The
threshold with increasing temperature is set by making the fixed
resistance equal in value to the thermistor resistance at the
desired trip temperature.
V_TH↑ = 2.5V and R1 = R2 (HOT)
To determine the value of the hysteresis resistor, R3, select the
value of thermistor resistance that corresponds to the desired
reset temperature.
R3
=
-¹---⁰----⁵----^•-----⁽--^R----¹-----–-----^R----²----⁾----–----^R----¹------^•----^R----²--
R1 + R2
Ω
(EQ. 11)
If the hysteresis resistor, R3, is not desired, the value of the
thermistor resistance at the reset temperature can be
determined from:
R1
=
----------²----^.-⁵-----^•----^R-----²-----------
2.5 – 10^–5 • R2
Ω
(NTC)
(EQ. 12)
R2
=
----------²----^.-⁵-----^•-----^R----¹------------
2.5 + 10^–5 • R1
Ω
(PTC)
(EQ. 13)
The OTS comparator may also be used to monitor signals other
than suggested above. It may also be used to monitor any
voltage signal for which an excess requires a response as
described above. Input or output voltage monitoring are
examples of this.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device.
A good ground plane must be employed. V_DD should be bypassed
directly to GND with good high frequency capacitance.
Typical Application
The Typical Application Schematic features the ISL6740 in an
unregulated half-bridge DC/DC converter configuration, often
referred to as a DC Transformer or Bus Regulator. The
ISL6740EVAL1 demonstration unit implements this design and is
available for evaluation.
The input voltage range is 48 ±10%VDC. The output is a nominal
12V when the input voltage is at 48V. Since this is an
unregulated topology, the output voltage will vary proportionately
with input voltage. The load regulation is a function of resistance
between the source and the converter output. The output is rated
at 8A.
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
Input Filtering: L₁, C₁, R₁
Half-Bridge Capacitors: C₂, C₃
Isolation Transformer: T₁
Primary Snubber: C₁₃, R₁₀
Start Bias Regulator: C_R3, R₂, R₇, C₆, Q₅, D₁
Supply Bypass Components: R₃, C₁₅, C₄, C₅
Main MOSFET Power Switch: QH, QL
Current Sense Network: T₂, C_R1, C_R2, R₅, R₆, R₁₁, C₁₀, C₁₄
Control Circuit: U₃, R_T1, R₁₄, R₁₉, R₁₃, R₁₅, R₁₇, R₁₈, C₁₆, C₁₈,
C₁₇
Output Rectification and Filtering: Q_R1, Q_R2, Q_R3, Q_R4, L₂, C₉, C₈
Secondary Snubber: R₈, R₉, C₁₁, C₁₂
FET Driver: U₁
ZVS Resonant Delay (Optional): L₃, C₇
Design Criteria
The following design requirements were selected:
Switching Frequency, Fsw: 235kHz
V_IN: 48 ±10%V
V_OUT: 12V (nominal) @ I_OUT = 8A
P_OUT: 100W
Efficiency: 95%
Ripple: 1%
Transformer Design
The design of a transformer for a half-bridge application is a
straight forward affair, although iterative. It is a process of many
compromises, and even experienced designers will produce
different designs when presented with identical requirements.
The iterative design process is not presented here for clarity.
14
FN9111.6
December 2, 2011