ISL6561 Datasheet, PDF (22/26 Pages) Intersil Corporation – Multi-Phase PWM Controller with Precision Rds(on) or DCR Differential Current Sensing for VR10.X Application

ISL6561
C₂
R_C ^CC
COMP
FB
C₁
R₁
R_FB
IDROOP
VDIFF
FIGURE 14. COMPENSATION CIRCUIT FOR ISL6561 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 13). Keep
a position available for C₂, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
nce selected, the compensation values in Equations 23
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equations 23 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 12). Keep
a position available for C₂, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
trailing edge jitter problem is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A type
III controller, as shown in Figure 14, provides the necessary
compensation.
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, f_HF. This pole can be used for added
noise rejection or to assure adequate attenuation at the error-
amplifier high-order pole and zero frequencies. A good general
rule is to chose f_HF = 10f₀, but it can be higher if desired.
Choosing f_HF to be lower than 10f₀ can cause problems with
too much phase shift below the system bandwidth.
In the solutions to the compensation equations, there is a single
degree of freedom. For the solutions presented in Equations
26, R_FB is selected arbitrarily. The remaining compensation
components are then selected according to Equations 26.
R₁
=
R_F
B
----------C-----⁽--E----S-----R-----⁾---------
LC – C(ESR)
C₁
=
-----L----C-----^–-----C-----⁽--E-----S----R-----⁾
R_FB
C₂
=
-----------------------0----.-7----5---V-----^I-^N-------------------------
(2π)²f₀f_HF LCR_FBV_PP
R_C = -0--V-.--7--^P-5---^P-V---^--_I^2-_N---^π---^-_--2²----_π^f--0-f--f_H--^H---_F-^F----L--L--C--C--R---_–--^F-1---^B_----
C_C
=
--0----.-7----5----V----^I--^N----^-2----^π----f--^H----^F--------L----C-----^–---1---^---
(2π)²f₀f_HF LCR_FBV_PP
(EQ. 26)
In Equations 26, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V_PP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 6 and Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter necessarily limits the system
transient response. The output capacitor must supply or sink
load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ∆V_MAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
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FN9098.5
May 12, 2005