ISL6561 Datasheet, PDF (15/26 Pages) Intersil Corporation – Multi-Phase PWM Controller with Precision Rds(on) or DCR Differential Current Sensing for VR10.X Application

ISL6561
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
VID4 VID3 VID2 VID1 VID0 VID12.5 VDAC
0
0
0
0
1
0
1.0625V
0
0
0
0
0
1
1.0750V
0
0
0
0
0
0
1.0875V
1
1
1
1
1
1
OFF
1
1
1
1
1
0
OFF
1
1
1
1
0
1
1.1000V
1
1
1
1
0
0
1.1125V
1
1
1
0
1
1
1.1250V
1
1
1
0
1
0
1.1375V
1
1
1
0
0
1
1.1500V
1
1
1
0
0
0
1.1625V
1
1
0
1
1
1
1.1750V
1
1
0
1
1
0
1.1875V
1
1
0
1
0
1
1.2000V
1
1
0
1
0
0
1.2125V
1
1
0
0
1
1
1.2250V
1
1
0
0
1
0
1.2475V
1
1
0
0
0
1
1.2500V
1
1
0
0
0
0
1.2625V
1
0
1
1
1
1
1.2750V
1
0
1
1
1
0
1.2875V
1
0
1
1
0
1
1.3000V
1
0
1
1
0
0
1.3125V
1
0
1
0
1
1
1.3250V
1
0
1
0
1
0
1.3375V
1
0
1
0
0
1
1.3500V
1
0
1
0
0
0
1.3625V
1
0
0
1
1
1
1.3750V
1
0
0
1
1
0
1.3875V
1
0
0
1
0
1
1.4000V
1
0
0
1
0
0
1.4125V
1
0
0
0
1
1
1.4250V
1
0
0
0
1
0
1.4375V
1
0
0
0
0
1
1.4500V
1
0
0
0
0
0
1.4625V
0
1
1
1
1
1
1.4750V
0
1
1
1
1
0
1.4875V
0
1
1
1
0
1
1.5000V
0
1
1
1
0
0
1.5125V
0
1
1
0
1
1
1.5250V
15
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
VID4 VID3 VID2 VID1 VID0 VID12.5 VDAC
0
1
1
0
1
0
1.5375V
0
1
1
0
0
1
1.5500V
0
1
1
0
0
0
1.5625V
0
1
0
1
1
1
1.5750V
0
1
0
1
1
0
1.5875V
0
1
0
1
0
1
1.600V
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to control the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, I_AVG , flows from FB through a
load-line regulation resistor, R_FB. The resulting voltage drop
across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
V_DROOP = I_AVG R_FB
(EQ. 8)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
derived by combining Equations 8 with the appropriate
sample current expression defined by the current sense
method employed.
V_OUT
=
V_REF
–
V_O
F
F
S
ET
–



I--_{O-----U----T--}
4
-----^R-----^X-------
R_ISEN

R _{F B}
(EQ. 9)
Where V_REF is the reference voltage, V_OFS is the
programmed offset voltage, V_OUT is the total output current
of the converter, R_ISEN is the sense resistor in the ISEN line,
and R_FB is the feedback resistor. R_X has a value of DCR,
r_DS(ON), or R_SENSE depending on the sensing method.
Output-Voltage Offset Programming
The ISL6561 allows the designer to accurately adjust the
offset voltage. When a resistor, R_OFS, is connected between
OFS and VCC, the voltage across it is regulated to 2.0V. This
causes a proportional current (I_OFS) to flow into OFS. If
R_OFS is connected to ground, the voltage across it is
regulated to 0.5V, and I_OFS flows out of OFS. A resistor
FN9098.5
May 12, 2005