ISL6561 Datasheet, PDF (16/26 Pages) Intersil Corporation – Multi-Phase PWM Controller with Precision Rds(on) or DCR Differential Current Sensing for VR10.X Application

ISL6561
between DAC and REF, R_REF, is selected so that the product
(I_OFS x R_REF) is equal to the desired offset voltage. These
functions are shown in Figures 8.
FB
DYNAMIC
VID D/A
DAC
R_REF
E/A
REF
VCC
or
GND
-
2.0V
+
+
0.5V
-
VCC
GND
R_OFS
OFS
ISL6561CR
FIGURE 8. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6561CR
As evident in Figure 8, the OFSOUT pin must be connected
to the REF pin for this current injection to function in
ISL6561CR. The current flowing through R_REF creates an
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to VCC):
R_OFS
=
-²-----^×-----^R----^R-----^E----^F--
V_OFFSET
(EQ. 10)
For Negative Offset (connect R_OFS to GND):
R_OFS
=
0_----._--5_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 11)
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6561 checks the VID inputs six times every switching
cycle. If the VID code is found to have has changed, the
controller waits half of a complete cycle before executing a
12.5mV change. If during the half-cycle wait period, the
difference between DAC level and the new VID code
changes, no change is made. If the VID code is more than 1
bit higher or lower than the DAC (not recommended), the
controller will execute 12.5mV changes six times per cycle
until VID and DAC are equal. It is for this reason that it is
important to carefully control the rate of VID stepping in 1-bit
increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R_REF and C_REF is required for an ISL6561
based voltage regulator. The selection of R_REF is based on
the desired offset as detailed above in Output-Voltage Offset
Programming. The selection of C_REF is based on the time
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T_VID, the relationship between the time constant of
R_REF and C_REF network and T_VID is given by Equation 12.
C_REF R_REF = 4 T_VID
(EQ. 12)
Typically R_REF is selected to be 1kΩ, so with a VID step
change rate of 5µs per bit, the value of C_REF is 22nF based
on Equation 12.
Temperature Compensation
Both the MOSFET r_DS(ON) and inductor DCR of inductor
vary in proportion to varying temperature. This means that a
circuit using r_DS(ON) or DCR to sense channel current is
subject to a corresponding error in current measurement. In
order to compensate for this temperature-related error, a
temperature compensation circuit is provided within
ISL6561. This circuit senses the internal IC temperature and,
based on a resistor-selectable scaling factor, adjust the
droop current ouput to the IDROOP pin. When the TCOMP
resistor is properly selected, the droop current can
accurately represent the load current to achieve a linear,
temperature-independant load line.
The value of the Tcomp resistor can be determined using
Equation 13.
R_TCOMP
=
---------^α------------
K_T K_TC
(EQ. 13)
In Equation 13, K_T is the temperature coupling coefficient
between the ISL6561 and the lower MOSFET or output
inductor. It represents how closely the controller temperature
16
FN9098.5
May 12, 2005