ISL6561 Datasheet, PDF (13/26 Pages) Intersil Corporation – Multi-Phase PWM Controller with Precision Rds(on) or DCR Differential Current Sensing for VR10.X Application

ISL6561
INDUCTOR DCR Sensing
An inductor has a distributed direct current winding
resistance (DCR). Consider the inductor DCR as a separate
lumped quantity as shown in Figure 4. The channel current,
I_L, flowing through the inductor, also passes through the
DCR. Equation 4 shows the s-domain equivalent voltage,
V_L, across the inductor.
V_L = I_L ⋅ (s ⋅ L + DCR)
(EQ. 4)
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 5.
The voltage on the capacitor, V_C, can be shown to be
proportional to the channel current I_L(see Equation 5).
V_C
=
-^--^s-----^â‹---^{D----------C-L}--------^R---------⁺-----¹---^-----^â‹---⁽--^D-----^C-----^R------^â‹---^I--^L---⁾
(s ⋅ RC + 1)
(EQ. 5)
If the R-C network components are selected such that the R-
C time constant matches the inductor L/DCR time constant,
then V_C is equal to the voltage drop across the DCR.
V_IN
I_L(s)
ISL6561
L
DCR
INDUCTOR
V_L
V_OUT
C_OUT
V_C(s)
PWM(n)
R
C
ISL6561 INTERNAL CIRCUIT
I_n
R_ISEN
SAMPLE
&
HOLD
+
-
ISEN
=
IL
---^D-----^C------^R-----
RISEN
ISEN-
ISEN+
FIGURE 4. DCR SENSING CONFIGURATION
The capacitor voltage, V_C, is replicated across the sense
resistor R_ISEN. so that the current flowing through the sense
resistor is proportional to the inductor current. Equation 6
shows that the relationship between the channel current and
the sensed current I_SEN, is driven by the value of the sense
resistor and the inductor DCR.
I_SEN
=
I_L
⋅
---^D----^C-----^R-----
R_ISEN
(EQ. 6)
Current Sampling
During the forced off-time following a PWM transition low, the
associated channel current sense amplifier reproduces a
signal , I_SEN, proportional to the inductor current, I_L.
Regardless of the current sense method, I_SEN is simply a
scaled version of the inductor current. Coincident with the
falling edge of the PWM signal, the sample and hold circuitry
samples I_SEN. This is illustrated in Figure 5. The sample
time, t_SAMP, is fixed and equal to 1/3 of the switching period,
t_SW. Therefore, the sample current, I_n, is proportional to the
t_SAMP
=
t_--S----W----
3
=
--------¹---------
3 ⋅ f_SW
(EQ. 7)
output current and held for one switching cycle. The sample
current is used for current balance, load-line regulation, and
overcurrent protection.
I_L
PWM
I_SEN
t_SAMP
SAMPLE CURRENT, I_n
SWITCHING PERIOD
TIME
FIGURE 5. SAMPLE AND HOLD TIMING
Channel-Current Balance
The sampled currents I_n, from each active channel are
summed together and divided by the number of active
channels. The resulting cycle average current, I_AVG,
provides a measure of the total load current demand on the
converter during each switching cycle. Channel current
balance is achieved by comparing the sampled current of
each channel to the cycle average current, and making an
appropriate adjustment to each channel pulse width based
on the error. Intersil’s patented current-balance method is
illustrated in Figure 6, with error correction for channel 1
represented. In the figure, the cycle average current
combines with the channel 1 sample, I₁, to create an error
signal I_ER. The filtered error signal modifies the pulse width
commanded by V_COMP to correct any unbalance and force
I_ER toward zero. The same method for error signal correction
is applied to each active channel.
13
FN9098.5
May 12, 2005