ISL62884C Datasheet, PDF (22/30 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6™ Mobile CPUs

ISL62884C
Layout Guidelines
Table 5 shows the layout considerations. The designators
refer to the reference designs shown in Figure 22.
TABLE 5. LAYOUT CONSIDERATIONS
NAME
LAYOUT CONSIDERATION
GND
Create analog ground plane underneath the controller and the analog signal processing components. Don’t let the
power ground plane overlap with the analog ground plane. Avoid noisy planes/traces (e.g.: phase node) from
crossing over/overlapping with the analog plane.
CLK_EN# No special consideration.
PGOOD No special consideration.
RBIAS Place the R_BIAS resistor (R₁₆) in general proximity of the controller. Low impedance connection to the analog ground
plane.
VW
COMP
FB
Place capacitor (C₄) across VW and COMP in close proximity of the controller.
Place compensator components (C₃, C₅, C₆ R₇, R₁₁, R₁₀ and C₁₁) in general proximity of the controller.
VSEN
RTN
Place the VSEN/RTN filter (C₁₂, C₁₃) in close proximity of the controller for good decoupling.
VDD A capacitor (C₁₆) decouples it to GND. Place it in close proximity of the controller.
DPRSTP# No special consideration.
ISUM-
ISUM+
Place the current sensing circuit in general proximity of the controller.
Place C₈₂ very close to the controller.
Place NTC thermistors R₄₂ next to inductor (L1) so it senses the inductor temperature correctly.
The power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signal traces in parallel
fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads.
Route R₆₃ to the phase-node side pad of inductor L1. Route the other current sensing trace to the output side pad
of inductor L1.
If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to
the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of
the inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-
CURRENT-
SENSING TRACES SENSING TRACES
VIN
BOOT
A capacitor (C₁₇) decouples it to GND. Place it in close proximity of the controller.
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
UGATE
PHASE
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE trace to the high-side MOSFET (Q2 and Q8) source pins
instead of general phase node copper.
VSSP
LGATE
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing VSSP to the low-side MOSFET (Q3) source pins instead of general
power ground plane for better performance.
VCCP A capacitor (C₂₂) decouples it to GND. Place it in close proximity of the controller.
VID0~6 No special consideration.
VR_ON No special consideration.
DPRSLPVR No special consideration.
Phase Node Minimize phase node copper area. Don’t let the phase node copper overlap with/getting close to other sensitive
traces. Cut the power ground plane to avoid overlapping with phase node copper.
Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C₂₇, C₃₃, Q2, Q3).
22
FN7591.0
March 16, 2010