ISL62884C Datasheet, PDF (18/30 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6™ Mobile CPUs

ISL62884C
A typical set of parameters that provide good
temperature compensation are: R_sum = 1.82kΩ,
R_p = 11kΩ, R_ntcs = 2.61kΩ and R_ntc = 10kΩ
(ERT-J1VR103J). The NTC network parameters may need
to be fine tuned on actual boards. One can apply full load
DC current and record the output voltage reading
immediately; then record the output voltage reading
again when the board has reached the thermal steady
state. A good NTC network can limit the output voltage
drift to within 2mV. It is recommended to follow the
Intersil evaluation board layout and current-sensing
network parameters to minimize engineering time.
V_Cn(s) also needs to represent real-time I_o(s) for the
controller to achieve good transient response. Transfer
function A_cs(s) has a pole ω_sns and a zero ω_L. One needs
to match ω_L and ω_sns so A_cs(s) is unity gain at all
frequencies. By forcing ω_L equal to ω_sns and solving for
the solution, Equation 11 gives C_n value.
C_n
=
------------------------------^L--------------------------------
-^R----ⁿ---^t--^c---ⁿ----^e---^t---^×-----^R----^s---^u----^m--
R_ntcnet + R_sum
×
DCR
(EQ. 11)
i_o
V_o
FIGURE 11. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
i_o
V_o
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN C_n IS
TOO SMALL
i_o
V_o
For example, given R_sum = 1.82kΩ, R_p = 11kΩ,
R_ntcs = 2.61kΩ, R_ntc = 10kΩ, DCR = 19.7mΩ and
L = 1.5µH, Equation 11 gives C_n = 0.055µF.
Assuming the compensator design is correct, Figure 11
shows the expected load transient response waveforms if
C_n is correctly selected. When the load current I_core has
a square change, the output voltage V_core also has a
square response.
If C_n value is too large or too small, V_Cn(s) will not
accurately represent real-time I_o(s) and will worsen the
transient response. Figure 12 shows the load transient
response when C_n is too small. V_core will sag excessively
upon load insertion and may create a system failure.
Figure 13 shows the transient response when C_n is too
large. V_core is sluggish in drooping to its final value.
There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU
reliability.
Figure 14 shows the output voltage ring back problem
during load transient response. The load current i_o has a
fast step change, but the inductor current i_L cannot
accurately follow. Instead, i_L responds in first order
system fashion due to the nature of current loop. The
ESR and ESL effect of the output capacitors makes the
output voltage V_o dip quickly upon load current change.
However, the controller regulates V_o according to the
droop current i_droop, which is a real-time representation
of i_L; therefore it pulls V_o back to the level dictated by i_L,
causing the ring back problem. This phenomenon is not
observed when the output capacitors have very low ESR
and ESL, such as all ceramic capacitors.
Figure 15 shows two optional circuits for reduction of the
ring back. R_ip and C_ip form an R-C branch in parallel with
R_i, providing a lower impedance path than R_i at the
beginning of i_o change. R_ip and C_ip do not have any
effect at steady state. Through proper selection of R_ip
and C_ip values, i_droop can resemble i_o rather than i_L, and
V_o will not ring back. The recommended value for R_ip is
100Ω. C_ip should be determined through tuning the load
transient response waveforms on an actual board. The
recommended range for C_ip is 100pF~2000pF. However,
it should be noted that the R_ip -C_ip branch may distort
the i_droop waveform. Instead of being triangular as the
real inductor current, i_droop may have sharp spikes,
which may adversely affect i_droop average value
detection and therefore may affect OCP accuracy. User
discretion is advised.
i_O
i_L
FIGURE 13. LOAD TRANSIENT RESPONSE WHEN C_n IS
TOO LARGE
V_O
RING
BACK
FIGURE 14. OUTPUT VOLTAGE RING BACK PROBLEM
18
FN7591.0
March 16, 2010