ISL62884C Datasheet, PDF (21/30 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6™ Mobile CPUs

ISL62884C
Q1
VIN
GATE ^Q2
DRIVER
L
VO
COUT
IO
LOAD LINE SLOPE
MOD
COMP
-
EA
+
VID
+
+
20Ω
CHANNEL B
LOOP GAIN =
CHANNEL A
ISOLATION
TRANSFORMER
CHANNEL A
CHANNEL B
NETWORK
ANALYZER _{EXCITATION OUTPUT}
FIGURE 19. LOOP GAIN T2(s) MEASUREMENT SET-UP
Optional Slew Rate Compensation Circuit
For 1-Tick VID Transition
Rdroop
R_vid Cvid
FB
Ivid
Vcore
OPTIONAL
Idroop_vid
COMP
E/A
Σ
DAC
VDAC
X1
INTERNAL TO
IC
VIDs
VID<0:6>
RTN
VSS
VSSSENSE
VID<0:6>
Vfb
Ivid
Vcore
Idroop_vid
FIGURE 20. OPTIONAL SLEW RATE COMPENSATION
CIRCUIT FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the
VIDs at a controlled slew rate, such as 1.25µs per tick
(12.5mV), controlling output voltage V_core slew rate at
10mV/µs.
Figure 20 shows the waveforms of 1-tick VID transition.
During 1-tick VID transition, the DAC output changes at
approximately 15mV/µs slew rate, but the DAC cannot
step through multiple VIDs to control the slew rate.
Instead, the control loop response speed determines
V_core slew rate. Ideally, V_core will follow the FB pin
voltage slew rate. However, the controller senses the
inductor current increase during the up transition, as the
I_{droop_vid} waveform shows, and will droop the output
voltage V_core accordingly, making V_core slew rate slow.
Similar behavior occurs during the down transition.
To control V_core slew rate during 1-tick VID transition,
one can add the R_vid-C_vid branch, whose current I_vid
cancels I_{droop_vid}.
When V_core increases, the time domain expression of the
induced I_droop change is as shown in Equation 26:
I_droop(t)
=
-^C----^o---^u----^t---^×----^L----^L--
R_droop
×
-^d---^V-----^c---^o---^r--^e-
dt
×
⎛
⎜⎜ ¹
⎝
–
e ^{-C----o----u---–-t--t-×-----L---L--}_{⎟⎟⎞}
⎠
(EQ. 26)
where C_out is the total output capacitance.
In the meantime, the R_vid-C_vid branch current I_vid time
domain expression is shown in Equation 27:
I_vid(t)
=
C_vid
×
d_----V_-----f-b--
dt
×
⎛
⎜
⎜
1
–
e
R^-----_v^----_i^-_d^----–-×^---t--C^-----_v^---_i^--_d^--_⎟⎞
⎟
⎝
⎠
(EQ. 27)
It is desired to let I_vid(t) cancel I_{droop_vid}(t). So there
are Equation 28:
C_vid
×
d_----V_-----f-b--
dt
=
-^C----^o---^u----^t---^×-----^L---^L-- × -^d---^V-----^c---^o---^r--^e-
R_droop
dt
(EQ. 28)
and Equation 29:
R_vid × C_vid = C_out × LL
(EQ. 29)
The result is Equation 30:
R_vid = R_droop
(EQ. 30)
and Equation 31:
C_vid
=
C_{-----o---u----t---}×_----L_----L_--
R_droop
×
-^d---^V-----^c---^o---^r--^e-
--------^d---^t--------
d_----V_-----f-b--
dt
(EQ. 31)
For example: given LL = 5.7mΩ, R_droop = 0.57kΩ,
C_out = 410µF, dV_core/dt = 10mV/µs and
dV_fb/dt = 15mV/µs, Equation 30 gives R_vid = 0.57kΩ
and Equation 31 gives C_vid = 2730pF.
It’s recommended to select the calculated R_vid value and
start with the calculated C_vid value and tweak it on the
actual board to get the best performance.
During normal transient response, the FB pin voltage is
held constant, therefore is virtual ground in small signal
sense. The R_vid-C_vid network is between the virtual
ground and the real ground, and hence has no effect on
transient response.
21
FN7591.0
March 16, 2010