ISL62884C Datasheet, PDF (12/30 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6™ Mobile CPUs

ISL62884C
Diode Emulation and Period Stretching
PHASE
UGATE
LGATE
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FIGURE 6. DIODE EMULATION
ISL62884C can operate in diode emulation (DE) mode to
improve light load efficiency. In DE mode, the low-side
MOSFET conducts when the current is flowing from
source to drain and doesn’t not allow reverse current,
emulating a diode. As shown in Figure 6, when LGATE is
on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage
drop across the ON-resistance. The ISL62884C monitors
the current through monitoring the phase node voltage.
It turns off LGATE when the phase node voltage reaches
zero to prevent the inductor current from reversing the
direction and creating unnecessary power loss.
If the load current is light enough, as Figure 7 shows, the
inductor current will reach and stay at zero before the
next phase node pulse, and the regulator is in
discontinuous conduction mode (DCM). If the load
current is heavy enough, the inductor current will never
reach 0A, and the regulator is in CCM although the
controller is in DE mode.
VCRS
CCM/DCM BOUNDARY
VW
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VCRS
VW ^{LIGHT DCM}
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VCRS
DEEP DCM
VW
VDD
VR_ON
DAC
10mV/µs
2.5mV/µs
90%VBOOT
800µs
VID
COMMAND
VOLTAGE
13 SWITCHING CYCLES
CLK_EN#
PGOOD
~7ms
FIGURE 8. SOFT-START WAVEFORMS FOR CPU VR
APPLICATION
Figure 7 shows the operation principle in diode emulation
mode at light load. The load gets incrementally lighter in
the three cases from top to bottom. The PWM on-time is
determined by the VW window size, therefore is the
same, making the inductor current triangle the same in
the three cases. The ISL62884C clamps the ripple
capacitor voltage V_crs in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit
V_crs, naturally stretching the switching period. The
inductor current triangles move further apart from each
other such that the inductor current average value is
equal to the load current. The reduced switching
frequency helps increase light load efficiency.
Start-Up Timing
With the controller's V_DD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 1.1V logic high threshold.
Figure 8 shows the typical start-up timing. The
ISL62884C uses digital soft-start to ramp up DAC to the
boot voltage of 1.2V at about 2.5mV/µs. Once the output
voltage is within 10% of the boot voltage for 13 PWM
cycles (43µs for frequency = 300kHz), CLK_EN# is
pulled low and DAC slews at 10mV/µs to the voltage set
by the VID pins. PGOOD is asserted high in
approximately 7ms. Similar results occur if VR_ON is tied
to V_DD, with the soft-start sequence starting 120µs after
V_DD crosses the POR threshold.
Voltage Regulation and Load Line
Implementation
After the start sequence, the ISL62884C regulates the
output voltage to the value set by the VID inputs per
Table 1. The ISL62884C will control the no-load output
voltage to an accuracy of ±0.5% over the range of
0.75V to 1.5V. A differential amplifier allows voltage
sensing for precise voltage regulation at the
microprocessor die.
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FIGURE 7. PERIOD STRETCHING
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FN7591.0
March 16, 2010