ISL6334ACRZ-T Datasheet, PDF (21/31 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features

ISL6334, ISL6334A
ISL6334, ISL6334A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
100kΩ
EN_PWR
9.1kΩ
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
0.875V
FIGURE 8. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
The soft-start time is the sum of the 4 periods as shown in
Equation 14.
t_SS = t_D1 + t_D2 + t_D3 + t_D4
(EQ. 14)
t_D1 is a fixed delay with the typical value as 1.36ms. t_D3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore, the minimum t_D3 is about 86µs.
During t_D2 and t_D4, ISL6334, ISL6334A digitally controls the
DAC voltage change at 6.25mV per step. The time for each
step is determined by the frequency of the soft-start
oscillator, which is defined by the resistor R_SS from SS pin to
GND. The second soft-start ramp time t_D2 and t_D4 can be
calculated based on Equations 15 and 16:
t_D2
=
-1---.--1---x----R----^S----^S--
6.25 x 25
(
μ
s
)
(EQ. 15)
t_D4
=
(_{---V----V----I--D-----}–_{-----1---.--1----})_{--x---R-----S----S--}
6.25 x 25
(
μ
s
)
(EQ. 16)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time t_D2 will be 704µs and the
second soft-start ramp time t_D4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t_D5. The
typical value for t_D5 is 85µs. Before the VR_RDY is
released, the controller disregards the PSI# input and
always operates in normal CCM PWM mode.
21
VOUT, 500mV/DIV
t_D1
t_D2 t_D3 t_D4 t_D5
EN_VTT
VR_RDY
500µs/DIV
FIGURE 9. SOFT-START WAVEFORMS
Current Sense Output
The current flowing out of the IMON pin is equal to the
sensed average current inside ISL6334, ISL6334A. In typical
applications, a resistor is placed from the IMON pin to GND
to generate a voltage, which is proportional to the load
current and the resistor value, as shown in Equation 17:
V_IOUT
=
--R----^I--^O-----^U----^T-
N
------R----^X-------
R_ISEN
I_LOAD
(EQ. 17)
where V_IMON is the voltage at the IMON pin, R_IMON is the
resistor between the IMON pin and GND, I_LOAD is the total
output current of the converter, R_ISEN is the sense resistor
connected to the ISEN+ pin, N is the active channel number,
and R_X is the DC resistance of the current sense element,
either the DCR of the inductor or R_SENSE depending on the
sensing method.
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.11V
under the maximum load current. If the IMON pin voltage is
higher than 1.11V, overcurrent shutdown will be triggered, as
described in “Overcurrent Protection” on page 22.
A small capacitor can be placed between the IMON pin and
GND to reduce the noise impact. If this pin is not used, tie it
to GND.
Fault Monitoring and Protection
The ISL6334, ISL6334A actively monitors output voltage and
current to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common power-good indicator is provided for linking
to external system monitors. The schematic in Figure 10
outlines the interaction between the fault monitors and the
VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output which
indicates that the soft-start period has completed and the
output voltage is within the regulated range. VR_RDY is
pulled low during shutdown and releases high after a
FN6482.2
February 1, 2013