ISL6334ACRZ-T Datasheet, PDF (19/31 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features

ISL6334, ISL6334A
TABLE 2. VR11 VID 8 BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
1 0 1 0 0 1 0 1 0.58125
1 0 1 0 0 1 1 0 0.57500
1 0 1 0 0 1 1 1 0.56875
1 0 1 0 1 0 0 0 0.56250
1 0 1 0 1 0 0 1 0.55625
1 0 1 0 1 0 1 0 0.55000
1 0 1 0 1 0 1 1 0.54375
1 0 1 0 1 1 0 0 0.53750
1 0 1 0 1 1 0 1 0.53125
1 0 1 0 1 1 1 0 0.52500
1 0 1 0 1 1 1 1 0.51875
1 0 1 1 0 0 0 0 0.51250
1 0 1 1 0 0 0 1 0.50625
1 0 1 1 0 0 1 0 0.50000
11111110
OFF
11111111
OFF
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
direction, which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 6, a current proportional to the average
current of all active channels, I_AVG, flows from FB through a
load-line regulation resistor R_FB. The resulting voltage drop
across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as shown in Equation 8:
V_DROOP = I_AVG R_FB
(EQ. 8)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed, as shown in Equation 9:
V_OUT
=
V_REF
–
V_O
F
S
–
⎛
⎜
⎝
I--_{L----O----A----D--}
N
------R----^X-------
R_ISEN
R_F
⎞
B_⎠⎟
(EQ. 9)
where V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_LOAD is the total output current
of the converter, R_ISEN is the sense resistor connected to
the ISEN+ pin, and R_FB is the feedback resistor, N is the
active channel number, and R_X is the DCR, or R_SENSE
depending on the sensing method.
Therefore, the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
R_LL
=
--R----^F----^B--
N
-----R-----^X-------
R_ISEN
(EQ. 10)
Output-Voltage Offset Programming
The ISL6334, ISL6334A allows the designer to accurately
adjust the offset voltage. When a resistor, R_OFS, is
connected between OFS to VCC, the voltage across it is
regulated to 1.6V. This causes a proportional current (I_OFS)
to flow into OFS. If R_OFS is connected to ground, the voltage
across it is regulated to 0.4V, and I_OFS flows out of OFS. A
resistor between DAC and REF, R_REF, is selected so that
the product (I_OFS x R_OFS) is equal to the desired offset
voltage. These functions are shown in Figure 7.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to calculate R_OFS:
For Positive Offset (connect R_OFS to VCC):
R_OFS
=
1_----._--6_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 11)
For Negative Offset (connect R_OFS to GND):
R_OFS
=
0_----._--4_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 12)
19
FN6482.2
February 1, 2013